Zephyr API Documentation
3.6.99
A Scalable Open Source RTOS
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#include <zephyr/types.h>
#include <zephyr/device.h>
#include <zephyr/toolchain.h>
#include <zephyr/sys/util.h>
Go to the source code of this file.
Data Structures | |
struct | i3c_ccc_target_payload |
Payload structure for Direct CCC to one target. More... | |
struct | i3c_ccc_payload |
Payload structure for one CCC transaction. More... | |
struct | i3c_ccc_events |
Payload for ENEC/DISEC CCC (Target Events Command). More... | |
struct | i3c_ccc_mwl |
Payload for SETMWL/GETMWL CCC (Set/Get Maximum Write Length). More... | |
struct | i3c_ccc_mrl |
Payload for SETMRL/GETMRL CCC (Set/Get Maximum Read Length). More... | |
struct | i3c_ccc_deftgts_active_controller |
The active controller part of payload for DEFTGTS CCC. More... | |
struct | i3c_ccc_deftgts_target |
The target device part of payload for DEFTGTS CCC. More... | |
struct | i3c_ccc_deftgts |
Payload for DEFTGTS CCC (Define List of Targets). More... | |
struct | i3c_ccc_address |
Payload for a single device address. More... | |
struct | i3c_ccc_getpid |
Payload for GETPID CCC (Get Provisioned ID). More... | |
struct | i3c_ccc_getbcr |
Payload for GETBCR CCC (Get Bus Characteristics Register). More... | |
struct | i3c_ccc_getdcr |
Payload for GETDCR CCC (Get Device Characteristics Register). More... | |
union | i3c_ccc_getstatus |
Payload for GETSTATUS CCC (Get Device Status). More... | |
struct | i3c_ccc_setbrgtgt_tgt |
One Bridged Target for SETBRGTGT payload. More... | |
struct | i3c_ccc_setbrgtgt |
Payload for SETBRGTGT CCC (Set Bridge Targets). More... | |
union | i3c_ccc_getmxds |
Payload for GETMXDS CCC (Get Max Data Speed). More... | |
union | i3c_ccc_getcaps |
Payload for GETCAPS CCC (Get Optional Feature Capabilities). More... | |
Macros | |
#define | I3C_CCC_BROADCAST_MAX_ID 0x7FU |
Maximum CCC ID for broadcast. | |
#define | I3C_CCC_ENEC(broadcast) ((broadcast) ? 0x00U : 0x80U) |
Enable Events Command. | |
#define | I3C_CCC_DISEC(broadcast) ((broadcast) ? 0x01U : 0x81U) |
Disable Events Command. | |
#define | I3C_CCC_ENTAS(as, broadcast) (((broadcast) ? 0x02U : 0x82U) + (as)) |
Enter Activity State. | |
#define | I3C_CCC_ENTAS0(broadcast) I3C_CCC_ENTAS(0, broadcast) |
Enter Activity State 0. | |
#define | I3C_CCC_ENTAS1(broadcast) I3C_CCC_ENTAS(1, broadcast) |
Enter Activity State 1. | |
#define | I3C_CCC_ENTAS2(broadcast) I3C_CCC_ENTAS(2, broadcast) |
Enter Activity State 2. | |
#define | I3C_CCC_ENTAS3(broadcast) I3C_CCC_ENTAS(3, broadcast) |
Enter Activity State 3. | |
#define | I3C_CCC_RSTDAA 0x06U |
Reset Dynamic Address Assignment (Broadcast) | |
#define | I3C_CCC_ENTDAA 0x07U |
Enter Dynamic Address Assignment (Broadcast) | |
#define | I3C_CCC_DEFTGTS 0x08U |
Define List of Targets (Broadcast) | |
#define | I3C_CCC_SETMWL(broadcast) ((broadcast) ? 0x09U : 0x89U) |
Set Max Write Length (Broadcast or Direct) | |
#define | I3C_CCC_SETMRL(broadcast) ((broadcast) ? 0x0AU : 0x8AU) |
Set Max Read Length (Broadcast or Direct) | |
#define | I3C_CCC_ENTTM 0x0BU |
Enter Test Mode (Broadcast) | |
#define | I3C_CCC_SETBUSCON 0x0CU |
Set Bus Context (Broadcast) | |
#define | I3C_CCC_ENDXFER(broadcast) ((broadcast) ? 0x12U : 0x92U) |
Data Transfer Ending Procedure Control. | |
#define | I3C_CCC_ENTHDR(x) (0x20U + (x)) |
Enter HDR Mode (HDR-DDR) (Broadcast) | |
#define | I3C_CCC_ENTHDR0 0x20U |
Enter HDR Mode 0 (HDR-DDR) (Broadcast) | |
#define | I3C_CCC_ENTHDR1 0x21U |
Enter HDR Mode 1 (HDR-TSP) (Broadcast) | |
#define | I3C_CCC_ENTHDR2 0x22U |
Enter HDR Mode 2 (HDR-TSL) (Broadcast) | |
#define | I3C_CCC_ENTHDR3 0x23U |
Enter HDR Mode 3 (HDR-BT) (Broadcast) | |
#define | I3C_CCC_ENTHDR4 0x24U |
Enter HDR Mode 4 (Broadcast) | |
#define | I3C_CCC_ENTHDR5 0x25U |
Enter HDR Mode 5 (Broadcast) | |
#define | I3C_CCC_ENTHDR6 0x26U |
Enter HDR Mode 6 (Broadcast) | |
#define | I3C_CCC_ENTHDR7 0x27U |
Enter HDR Mode 7 (Broadcast) | |
#define | I3C_CCC_SETXTIME(broadcast) ((broadcast) ? 0x28U : 0x98U) |
Exchange Timing Information (Broadcast or Direct) | |
#define | I3C_CCC_SETAASA 0x29U |
Set All Addresses to Static Addresses (Broadcast) | |
#define | I3C_CCC_RSTACT(broadcast) ((broadcast) ? 0x2AU : 0x9AU) |
Target Reset Action. | |
#define | I3C_CCC_DEFGRPA 0x2BU |
Define List of Group Address (Broadcast) | |
#define | I3C_CCC_RSTGRPA(broadcast) ((broadcast) ? 0x2CU : 0x9CU) |
Reset Group Address. | |
#define | I3C_CCC_MLANE(broadcast) ((broadcast) ? 0x2DU : 0x9DU) |
Multi-Lane Data Transfer Control (Broadcast) | |
#define | I3C_CCC_VENDOR(broadcast, id) ((id) + ((broadcast) ? 0x61U : 0xE0U)) |
Vendor/Standard Extension. | |
#define | I3C_CCC_SETDASA 0x87U |
Set Dynamic Address from Static Address (Direct) | |
#define | I3C_CCC_SETNEWDA 0x88U |
Set New Dynamic Address (Direct) | |
#define | I3C_CCC_GETMWL 0x8BU |
Get Max Write Length (Direct) | |
#define | I3C_CCC_GETMRL 0x8CU |
Get Max Read Length (Direct) | |
#define | I3C_CCC_GETPID 0x8DU |
Get Provisioned ID (Direct) | |
#define | I3C_CCC_GETBCR 0x8EU |
Get Bus Characteristics Register (Direct) | |
#define | I3C_CCC_GETDCR 0x8FU |
Get Device Characteristics Register (Direct) | |
#define | I3C_CCC_GETSTATUS 0x90U |
Get Device Status (Direct) | |
#define | I3C_CCC_GETACCCR 0x91U |
Get Accept Controller Role (Direct) | |
#define | I3C_CCC_SETBRGTGT 0x93U |
Set Bridge Targets (Direct) | |
#define | I3C_CCC_GETMXDS 0x94U |
Get Max Data Speed (Direct) | |
#define | I3C_CCC_GETCAPS 0x95U |
Get Optional Feature Capabilities (Direct) | |
#define | I3C_CCC_SETROUTE 0x96U |
Set Route (Direct) | |
#define | I3C_CCC_D2DXFER 0x97U |
Device to Device(s) Tunneling Control (Direct) | |
#define | I3C_CCC_GETXTIME 0x99U |
Get Exchange Timing Information (Direct) | |
#define | I3C_CCC_SETGRPA 0x9BU |
Set Group Address (Direct) | |
#define | I3C_CCC_ENEC_EVT_ENINTR BIT(0) |
Enable Events (ENEC) - Target Interrupt Requests. | |
#define | I3C_CCC_ENEC_EVT_ENCR BIT(1) |
Enable Events (ENEC) - Controller Role Requests. | |
#define | I3C_CCC_ENEC_EVT_ENHJ BIT(3) |
Enable Events (ENEC) - Hot-Join Event. | |
#define | I3C_CCC_ENEC_EVT_ALL (I3C_CCC_ENEC_EVT_ENINTR | I3C_CCC_ENEC_EVT_ENCR | I3C_CCC_ENEC_EVT_ENHJ) |
#define | I3C_CCC_DISEC_EVT_DISINTR BIT(0) |
Disable Events (DISEC) - Target Interrupt Requests. | |
#define | I3C_CCC_DISEC_EVT_DISCR BIT(1) |
Disable Events (DISEC) - Controller Role Requests. | |
#define | I3C_CCC_DISEC_EVT_DISHJ BIT(3) |
Disable Events (DISEC) - Hot-Join Event. | |
#define | I3C_CCC_DISEC_EVT_ALL (I3C_CCC_DISEC_EVT_DISINTR | I3C_CCC_DISEC_EVT_DISCR | I3C_CCC_DISEC_EVT_DISHJ) |
#define | I3C_CCC_EVT_INTR BIT(0) |
Events - Target Interrupt Requests. | |
#define | I3C_CCC_EVT_CR BIT(1) |
Events - Controller Role Requests. | |
#define | I3C_CCC_EVT_HJ BIT(3) |
Events - Hot-Join Event. | |
#define | I3C_CCC_EVT_ALL (I3C_CCC_EVT_INTR | I3C_CCC_EVT_CR | I3C_CCC_EVT_HJ) |
Bitmask for all events. | |
#define | I3C_CCC_GETSTATUS_PROTOCOL_ERR BIT(5) |
GETSTATUS Format 1 - Protocol Error bit. | |
#define | I3C_CCC_GETSTATUS_ACTIVITY_MODE_SHIFT 6 |
GETSTATUS Format 1 - Activity Mode bit shift value. | |
#define | I3C_CCC_GETSTATUS_ACTIVITY_MODE_MASK (0x03U << I3C_CCC_GETSTATUS_ACTIVITY_MODE_SHIFT) |
GETSTATUS Format 1 - Activity Mode bitmask. | |
#define | I3C_CCC_GETSTATUS_ACTIVITY_MODE(status) |
GETSTATUS Format 1 - Activity Mode. | |
#define | I3C_CCC_GETSTATUS_NUM_INT_SHIFT 0 |
GETSTATUS Format 1 - Number of Pending Interrupts bit shift value. | |
#define | I3C_CCC_GETSTATUS_NUM_INT_MASK (0x0FU << I3C_CCC_GETSTATUS_NUM_INT_SHIFT) |
GETSTATUS Format 1 - Number of Pending Interrupts bitmask. | |
#define | I3C_CCC_GETSTATUS_NUM_INT(status) |
GETSTATUS Format 1 - Number of Pending Interrupts. | |
#define | I3C_CCC_GETSTATUS_PRECR_DEEP_SLEEP_DETECTED BIT(0) |
GETSTATUS Format 2 - PERCR - Deep Sleep Detected bit. | |
#define | I3C_CCC_GETSTATUS_PRECR_HANDOFF_DELAY_NACK BIT(1) |
GETSTATUS Format 2 - PERCR - Handoff Delay NACK. | |
#define | I3C_CCC_GETMXDS_MAX_SDR_FSCL_MAX 0 |
Get Max Data Speed (GETMXDS) - Default Max Sustained Data Rate. | |
#define | I3C_CCC_GETMXDS_MAX_SDR_FSCL_8MHZ 1 |
Get Max Data Speed (GETMXDS) - 8MHz Max Sustained Data Rate. | |
#define | I3C_CCC_GETMXDS_MAX_SDR_FSCL_6MHZ 2 |
Get Max Data Speed (GETMXDS) - 6MHz Max Sustained Data Rate. | |
#define | I3C_CCC_GETMXDS_MAX_SDR_FSCL_4MHZ 3 |
Get Max Data Speed (GETMXDS) - 4MHz Max Sustained Data Rate. | |
#define | I3C_CCC_GETMXDS_MAX_SDR_FSCL_2MHZ 4 |
Get Max Data Speed (GETMXDS) - 2MHz Max Sustained Data Rate. | |
#define | I3C_CCC_GETMXDS_TSCO_8NS 0 |
Get Max Data Speed (GETMXDS) - Clock to Data Turnaround <= 8ns. | |
#define | I3C_CCC_GETMXDS_TSCO_9NS 1 |
Get Max Data Speed (GETMXDS) - Clock to Data Turnaround <= 9ns. | |
#define | I3C_CCC_GETMXDS_TSCO_10NS 2 |
Get Max Data Speed (GETMXDS) - Clock to Data Turnaround <= 10ns. | |
#define | I3C_CCC_GETMXDS_TSCO_11NS 3 |
Get Max Data Speed (GETMXDS) - Clock to Data Turnaround <= 11ns. | |
#define | I3C_CCC_GETMXDS_TSCO_12NS 4 |
Get Max Data Speed (GETMXDS) - Clock to Data Turnaround <= 12ns. | |
#define | I3C_CCC_GETMXDS_TSCO_GT_12NS 7 |
Get Max Data Speed (GETMXDS) - Clock to Data Turnaround > 12ns. | |
#define | I3C_CCC_GETMXDS_MAXWR_DEFINING_BYTE_SUPPORT BIT(3) |
Get Max Data Speed (GETMXDS) - maxWr - Optional Defining Byte Support. | |
#define | I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL_SHIFT 0 |
Get Max Data Speed (GETMXDS) - Max Sustained Data Rate bit shift value. | |
#define | I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL_MASK (0x07U << I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL_SHIFT) |
Get Max Data Speed (GETMXDS) - Max Sustained Data Rate bitmask. | |
#define | I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL(maxwr) |
Get Max Data Speed (GETMXDS) - maxWr - Max Sustained Data Rate. | |
#define | I3C_CCC_GETMXDS_MAXRD_W2R_PERMITS_STOP_BETWEEN BIT(6) |
Get Max Data Speed (GETMXDS) - maxRd - Write-to-Read Permits Stop Between. | |
#define | I3C_CCC_GETMXDS_MAXRD_TSCO_SHIFT 3 |
Get Max Data Speed (GETMXDS) - maxRd - Clock to Data Turnaround bit shift value. | |
#define | I3C_CCC_GETMXDS_MAXRD_TSCO_MASK (0x07U << I3C_CCC_GETMXDS_MAXRD_TSCO_SHIFT) |
Get Max Data Speed (GETMXDS) - maxRd - Clock to Data Turnaround bitmask. | |
#define | I3C_CCC_GETMXDS_MAXRD_TSCO(maxrd) |
Get Max Data Speed (GETMXDS) - maxRd - Clock to Data Turnaround. | |
#define | I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL_SHIFT 0 |
Get Max Data Speed (GETMXDS) - maxRd - Max Sustained Data Rate bit shift value. | |
#define | I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL_MASK (0x07U << I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL_SHIFT) |
Get Max Data Speed (GETMXDS) - maxRd - Max Sustained Data Rate bitmask. | |
#define | I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL(maxrd) |
Get Max Data Speed (GETMXDS) - maxRd - Max Sustained Data Rate. | |
#define | I3C_CCC_GETMXDS_CRDHLY1_SET_BUS_ACT_STATE BIT(2) |
Get Max Data Speed (GETMXDS) - CRDHLY1 - Set Bus Activity State bit shift value. | |
#define | I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE_SHIFT 0 |
Get Max Data Speed (GETMXDS) - CRDHLY1 - Controller Handoff Activity State bit shift value. | |
#define | I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE_MASK (0x03U << I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE_SHIFT) |
Get Max Data Speed (GETMXDS) - CRDHLY1 - Controller Handoff Activity State bitmask. | |
#define | I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE(crhdly1) |
Get Max Data Speed (GETMXDS) - CRDHLY1 - Controller Handoff Activity State. | |
#define | I3C_CCC_GETCAPS1_HDR_DDR BIT(0) |
Get Optional Feature Capabilities Byte 1 (GETCAPS) Format 1 - HDR-DDR mode bit. | |
#define | I3C_CCC_GETCAPS1_HDR_TSP BIT(1) |
Get Optional Feature Capabilities Byte 1 (GETCAPS) Format 1 - HDR-TSP mode bit. | |
#define | I3C_CCC_GETCAPS1_HDR_TSL BIT(2) |
Get Optional Feature Capabilities Byte 1 (GETCAPS) Format 1 - HDR-TSL mode bit. | |
#define | I3C_CCC_GETCAPS1_HDR_BT BIT(3) |
Get Optional Feature Capabilities Byte 1 (GETCAPS) Format 1 - HDR-BT mode bit. | |
#define | I3C_CCC_GETCAPS1_HDR_MODE(x) BIT(x) |
Get Optional Feature Capabilities Byte 1 (GETCAPS) - HDR Mode. | |
#define | I3C_CCC_GETCAPS1_HDR_MODE0 BIT(0) |
Get Optional Feature Capabilities Byte 1 (GETCAPS) Format 1 - HDR Mode 0. | |
#define | I3C_CCC_GETCAPS1_HDR_MODE1 BIT(1) |
Get Optional Feature Capabilities Byte 1 (GETCAPS) Format 1 - HDR Mode 1. | |
#define | I3C_CCC_GETCAPS1_HDR_MODE2 BIT(2) |
Get Optional Feature Capabilities Byte 1 (GETCAPS) Format 1 - HDR Mode 2. | |
#define | I3C_CCC_GETCAPS1_HDR_MODE3 BIT(3) |
Get Optional Feature Capabilities Byte 1 (GETCAPS) Format 1 - HDR Mode 3. | |
#define | I3C_CCC_GETCAPS1_HDR_MODE4 BIT(4) |
Get Optional Feature Capabilities Byte 1 (GETCAPS) Format 1 - HDR Mode 4. | |
#define | I3C_CCC_GETCAPS1_HDR_MODE5 BIT(5) |
Get Optional Feature Capabilities Byte 1 (GETCAPS) Format 1 - HDR Mode 5. | |
#define | I3C_CCC_GETCAPS1_HDR_MODE6 BIT(6) |
Get Optional Feature Capabilities Byte 1 (GETCAPS) Format 1 - HDR Mode 6. | |
#define | I3C_CCC_GETCAPS1_HDR_MODE7 BIT(7) |
Get Optional Feature Capabilities Byte 1 (GETCAPS) Format 1 - HDR Mode 7. | |
#define | I3C_CCC_GETCAPS2_HDRDDR_WRITE_ABORT BIT(6) |
Get Optional Feature Capabilities Byte 2 (GETCAPS) Format 1 - HDR-DDR Write Abort bit. | |
#define | I3C_CCC_GETCAPS2_HDRDDR_ABORT_CRC BIT(7) |
Get Optional Feature Capabilities Byte 2 (GETCAPS) Format 1 - HDR-DDR Abort CRC bit. | |
#define | I3C_CCC_GETCAPS2_GRPADDR_CAP_SHIFT 4 |
Get Optional Feature Capabilities Byte 2 (GETCAPS) Format 1 - Group Address Capabilities bit shift value. | |
#define | I3C_CCC_GETCAPS2_GRPADDR_CAP_MASK (0x03U << I3C_CCC_GETCAPS2_GRPADDR_CAP_SHIFT) |
Get Optional Feature Capabilities Byte 2 (GETCAPS) Format 1 - Group Address Capabilities bitmask. | |
#define | I3C_CCC_GETCAPS2_GRPADDR_CAP(getcaps2) |
Get Optional Feature Capabilities Byte 2 (GETCAPS) Format 1 - Group Address Capabilities. | |
#define | I3C_CCC_GETCAPS2_SPEC_VER_SHIFT 0 |
Get Optional Feature Capabilities Byte 2 (GETCAPS) Format 1 - I3C 1.x Specification Version bit shift value. | |
#define | I3C_CCC_GETCAPS2_SPEC_VER_MASK (0x0FU << I3C_CCC_GETCAPS2_SPEC_VER_SHIFT) |
Get Optional Feature Capabilities Byte 2 (GETCAPS) Format 1 - I3C 1.x Specification Version bitmask. | |
#define | I3C_CCC_GETCAPS2_SPEC_VER(getcaps2) |
Get Optional Feature Capabilities Byte 2 (GETCAPS) Format 1 - I3C 1.x Specification Version. | |
#define | I3C_CCC_GETCAPS3_MLANE_SUPPORT BIT(0) |
Get Optional Feature Capabilities Byte 3 (GETCAPS) Format 1 - Multi-Lane Data Transfer Support bit. | |
#define | I3C_CCC_GETCAPS3_D2DXFER_SUPPORT BIT(1) |
Get Optional Feature Capabilities Byte 3 (GETCAPS) Format 1 - Device to Device Transfer (D2DXFER) Support bit. | |
#define | I3C_CCC_GETCAPS3_D2DXFER_IBI_CAPABLE BIT(2) |
Get Optional Feature Capabilities Byte 3 (GETCAPS) Format 1 - Device to Device Transfer (D2DXFER) IBI Capable bit. | |
#define | I3C_CCC_GETCAPS3_GETCAPS_DEFINING_BYTE_SUPPORT BIT(3) |
Get Optional Feature Capabilities Byte 3 (GETCAPS) Format 1 - Defining Byte Support in GETCAPS bit. | |
#define | I3C_CCC_GETCAPS3_GETSTATUS_DEFINING_BYTE_SUPPORT BIT(4) |
Get Optional Feature Capabilities Byte 3 (GETCAPS) Format 1 - Defining Byte Support in GETSTATUS bit. | |
#define | I3C_CCC_GETCAPS3_HDRBT_CRC32_SUPPORT BIT(5) |
Get Optional Feature Capabilities Byte 3 (GETCAPS) Format 1 - HDR-BT CRC-32 Support bit. | |
#define | I3C_CCC_GETCAPS3_IBI_MDR_PENDING_READ_NOTIFICATION BIT(6) |
Get Optional Feature Capabilities Byte 3 (GETCAPS) Format 1 - IBI MDB Support for Pending Read Notification bit. | |
#define | I3C_CCC_GETCAPS_TESTPAT1 0xA5 |
Get Fixed Test Pattern (GETCAPS) Format 2 - Fixed Test Pattern Byte 1. | |
#define | I3C_CCC_GETCAPS_TESTPAT2 0x5A |
Get Fixed Test Pattern (GETCAPS) Format 2 - Fixed Test Pattern Byte 2. | |
#define | I3C_CCC_GETCAPS_TESTPAT3 0xA5 |
Get Fixed Test Pattern (GETCAPS) Format 2 - Fixed Test Pattern Byte 3. | |
#define | I3C_CCC_GETCAPS_TESTPAT4 0x5A |
Get Fixed Test Pattern (GETCAPS) Format 2 - Fixed Test Pattern Byte 4. | |
#define | I3C_CCC_GETCAPS_TESTPAT 0xA55AA55A |
Get Fixed Test Pattern (GETCAPS) Format 2 - Fixed Test Pattern Word in Big Endian. | |
#define | I3C_CCC_GETCAPS_CRCAPS1_HJ_SUPPORT BIT(0) |
Get Controller Handoff Capabilities Byte 1 (GETCAPS) Format 2 - Hot-Join Support. | |
#define | I3C_CCC_GETCAPS_CRCAPS1_GRP_MANAGEMENT_SUPPORT BIT(1) |
Get Controller Handoff Capabilities Byte 1 (GETCAPS) Format 2 - Group Management Support. | |
#define | I3C_CCC_GETCAPS_CRCAPS1_ML_SUPPORT BIT(2) |
Get Controller Handoff Capabilities Byte 1 (GETCAPS) Format 2 - Multi-Lane Support. | |
#define | I3C_CCC_GETCAPS_CRCAPS2_IBI_TIR_SUPPORT BIT(0) |
Get Controller Handoff Capabilities Byte 2 (GETCAPS) Format 2 - In-Band Interrupt Support. | |
#define | I3C_CCC_GETCAPS_CRCAPS2_CONTROLLER_PASSBACK BIT(1) |
Get Controller Handoff Capabilities Byte 2 (GETCAPS) Format 2 - Controller Pass-Back. | |
#define | I3C_CCC_GETCAPS_CRCAPS2_DEEP_SLEEP_CAPABLE BIT(2) |
Get Controller Handoff Capabilities Byte 2 (GETCAPS) Format 2 - Deep Sleep Capable. | |
#define | I3C_CCC_GETCAPS_CRCAPS2_DELAYED_CONTROLLER_HANDOFF BIT(3) |
Get Controller Handoff Capabilities Byte 2 (GETCAPS) Format 2 - Deep Sleep Capable. | |
#define | I3C_CCC_GETCAPS_VTCAP1_VITRUAL_TARGET_TYPE_SHIFT 0 |
Get Capabilities (GETCAPS) - VTCAP1 - Virtual Target Type bit shift value. | |
#define | I3C_CCC_GETCAPS_VTCAP1_VITRUAL_TARGET_TYPE_MASK (0x07U << I3C_CCC_GETCAPS_VTCAP1_VITRUAL_TARGET_TYPE_SHIFT) |
Get Capabilities (GETCAPS) - VTCAP1 - Virtual Target Type bitmask. | |
#define | I3C_CCC_GETCAPS_VTCAP1_VITRUAL_TARGET_TYPE(vtcap1) |
Get Capabilities (GETCAPS) - VTCAP1 - Virtual Target Type. | |
#define | I3C_CCC_GETCAPS_VTCAP1_SIDE_EFFECTS BIT(4) |
Get Virtual Target Capabilities Byte 1 (GETCAPS) Format 2 - Side Effects. | |
#define | I3C_CCC_GETCAPS_VTCAP1_SHARED_PERIPH_DETECT BIT(5) |
Get Virtual Target Capabilities Byte 1 (GETCAPS) Format 2 - Shared Peripheral Detect. | |
#define | I3C_CCC_GETCAPS_VTCAP2_INTERRUPT_REQUESTS_SHIFT 0 |
Get Capabilities (GETCAPS) - VTCAP2 - Interrupt Requests bit shift value. | |
#define | I3C_CCC_GETCAPS_VTCAP2_INTERRUPT_REQUESTS_MASK (0x03U << I3C_CCC_GETCAPS_VTCAP2_INTERRUPT_REQUESTS_SHIFT) |
Get Capabilities (GETCAPS) - VTCAP2 - Interrupt Requests bitmask. | |
#define | I3C_CCC_GETCAPS_VTCAP2_INTERRUPT_REQUESTS(vtcap2) |
Get Capabilities (GETCAPS) - VTCAP2 - Interrupt Requests. | |
#define | I3C_CCC_GETCAPS_VTCAP2_ADDRESS_REMAPPING BIT(2) |
Get Virtual Target Capabilities Byte 2 (GETCAPS) Format 2 - Address Remapping. | |
#define | I3C_CCC_GETCAPS_VTCAP2_BUS_CONTEXT_AND_COND_SHIFT 3 |
Get Capabilities (GETCAPS) - VTCAP2 - Bus Context and Condition bit shift value. | |
#define | I3C_CCC_GETCAPS_VTCAP2_BUS_CONTEXT_AND_COND_MASK (0x03U << I3C_CCC_GETCAPS_VTCAP2_BUS_CONTEXT_AND_COND_SHIFT) |
Get Capabilities (GETCAPS) - VTCAP2 - Bus Context and Condition bitmask. | |
#define | I3C_CCC_GETCAPS_VTCAP2_BUS_CONTEXT_AND_COND(vtcap2) |
Get Capabilities (GETCAPS) - VTCAP2 - Bus Context and Condition. | |
Functions | |
static bool | i3c_ccc_is_payload_broadcast (const struct i3c_ccc_payload *payload) |
Test if I3C CCC payload is for broadcast. | |
int | i3c_ccc_do_getbcr (struct i3c_device_desc *target, struct i3c_ccc_getbcr *bcr) |
Get BCR from a target. | |
int | i3c_ccc_do_getdcr (struct i3c_device_desc *target, struct i3c_ccc_getdcr *dcr) |
Get DCR from a target. | |
int | i3c_ccc_do_getpid (struct i3c_device_desc *target, struct i3c_ccc_getpid *pid) |
Get PID from a target. | |
int | i3c_ccc_do_rstact_all (const struct device *controller, enum i3c_ccc_rstact_defining_byte action) |
Broadcast RSTACT to reset I3C Peripheral. | |
int | i3c_ccc_do_rstdaa_all (const struct device *controller) |
Broadcast RSTDAA to reset dynamic addresses for all targets. | |
int | i3c_ccc_do_setdasa (const struct i3c_device_desc *target) |
Set Dynamic Address from Static Address for a target. | |
int | i3c_ccc_do_setnewda (const struct i3c_device_desc *target, struct i3c_ccc_address new_da) |
Set New Dynamic Address for a target. | |
int | i3c_ccc_do_events_all_set (const struct device *controller, bool enable, struct i3c_ccc_events *events) |
Broadcast ENEC/DISEC to enable/disable target events. | |
int | i3c_ccc_do_events_set (struct i3c_device_desc *target, bool enable, struct i3c_ccc_events *events) |
Direct CCC ENEC/DISEC to enable/disable target events. | |
int | i3c_ccc_do_setmwl_all (const struct device *controller, const struct i3c_ccc_mwl *mwl) |
Broadcast SETMWL to Set Maximum Write Length. | |
int | i3c_ccc_do_setmwl (const struct i3c_device_desc *target, const struct i3c_ccc_mwl *mwl) |
Single target SETMWL to Set Maximum Write Length. | |
int | i3c_ccc_do_getmwl (const struct i3c_device_desc *target, struct i3c_ccc_mwl *mwl) |
Single target GETMWL to Get Maximum Write Length. | |
int | i3c_ccc_do_setmrl_all (const struct device *controller, const struct i3c_ccc_mrl *mrl, bool has_ibi_size) |
Broadcast SETMRL to Set Maximum Read Length. | |
int | i3c_ccc_do_setmrl (const struct i3c_device_desc *target, const struct i3c_ccc_mrl *mrl) |
Single target SETMRL to Set Maximum Read Length. | |
int | i3c_ccc_do_getmrl (const struct i3c_device_desc *target, struct i3c_ccc_mrl *mrl) |
Single target GETMRL to Get Maximum Read Length. | |
int | i3c_ccc_do_getstatus (const struct i3c_device_desc *target, union i3c_ccc_getstatus *status, enum i3c_ccc_getstatus_fmt fmt, enum i3c_ccc_getstatus_defbyte defbyte) |
Single target GETSTATUS to Get Target Status. | |
static int | i3c_ccc_do_getstatus_fmt1 (const struct i3c_device_desc *target, union i3c_ccc_getstatus *status) |
Single target GETSTATUS to Get Target Status (Format 1). | |
static int | i3c_ccc_do_getstatus_fmt2 (const struct i3c_device_desc *target, union i3c_ccc_getstatus *status, enum i3c_ccc_getstatus_defbyte defbyte) |
Single target GETSTATUS to Get Target Status (Format 2). | |
int | i3c_ccc_do_getcaps (const struct i3c_device_desc *target, union i3c_ccc_getcaps *caps, enum i3c_ccc_getcaps_fmt fmt, enum i3c_ccc_getcaps_defbyte defbyte) |
Single target GETCAPS to Get Target Status. | |
static int | i3c_ccc_do_getcaps_fmt1 (const struct i3c_device_desc *target, union i3c_ccc_getcaps *caps) |
Single target GETCAPS to Get Capabilities (Format 1). | |
static int | i3c_ccc_do_getcaps_fmt2 (const struct i3c_device_desc *target, union i3c_ccc_getcaps *caps, enum i3c_ccc_getcaps_defbyte defbyte) |
Single target GETCAPS to Get Capabilities (Format 2). | |