Zephyr API Documentation  3.6.99
A Scalable Open Source RTOS
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ccc.h
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1/*
2 * Copyright 2022 Intel Corporation
3 * Copyright 2023 Meta Platforms, Inc. and its affiliates
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#ifndef ZEPHYR_INCLUDE_DRIVERS_I3C_CCC_H_
9#define ZEPHYR_INCLUDE_DRIVERS_I3C_CCC_H_
10
18#include <zephyr/types.h>
19#include <zephyr/device.h>
20#include <zephyr/toolchain.h>
21#include <zephyr/sys/util.h>
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
28#define I3C_CCC_BROADCAST_MAX_ID 0x7FU
29
35#define I3C_CCC_ENEC(broadcast) ((broadcast) ? 0x00U : 0x80U)
36
42#define I3C_CCC_DISEC(broadcast) ((broadcast) ? 0x01U : 0x81U)
43
50#define I3C_CCC_ENTAS(as, broadcast) (((broadcast) ? 0x02U : 0x82U) + (as))
51
57#define I3C_CCC_ENTAS0(broadcast) I3C_CCC_ENTAS(0, broadcast)
58
64#define I3C_CCC_ENTAS1(broadcast) I3C_CCC_ENTAS(1, broadcast)
65
71#define I3C_CCC_ENTAS2(broadcast) I3C_CCC_ENTAS(2, broadcast)
72
78#define I3C_CCC_ENTAS3(broadcast) I3C_CCC_ENTAS(3, broadcast)
79
81#define I3C_CCC_RSTDAA 0x06U
82
84#define I3C_CCC_ENTDAA 0x07U
85
87#define I3C_CCC_DEFTGTS 0x08U
88
94#define I3C_CCC_SETMWL(broadcast) ((broadcast) ? 0x09U : 0x89U)
95
101#define I3C_CCC_SETMRL(broadcast) ((broadcast) ? 0x0AU : 0x8AU)
102
104#define I3C_CCC_ENTTM 0x0BU
105
107#define I3C_CCC_SETBUSCON 0x0CU
108
114#define I3C_CCC_ENDXFER(broadcast) ((broadcast) ? 0x12U : 0x92U)
115
117#define I3C_CCC_ENTHDR(x) (0x20U + (x))
118
120#define I3C_CCC_ENTHDR0 0x20U
121
123#define I3C_CCC_ENTHDR1 0x21U
124
126#define I3C_CCC_ENTHDR2 0x22U
127
129#define I3C_CCC_ENTHDR3 0x23U
130
132#define I3C_CCC_ENTHDR4 0x24U
133
135#define I3C_CCC_ENTHDR5 0x25U
136
138#define I3C_CCC_ENTHDR6 0x26U
139
141#define I3C_CCC_ENTHDR7 0x27U
142
148#define I3C_CCC_SETXTIME(broadcast) ((broadcast) ? 0x28U : 0x98U)
149
151#define I3C_CCC_SETAASA 0x29U
152
158#define I3C_CCC_RSTACT(broadcast) ((broadcast) ? 0x2AU : 0x9AU)
159
161#define I3C_CCC_DEFGRPA 0x2BU
162
168#define I3C_CCC_RSTGRPA(broadcast) ((broadcast) ? 0x2CU : 0x9CU)
169
171#define I3C_CCC_MLANE(broadcast) ((broadcast) ? 0x2DU : 0x9DU)
172
179#define I3C_CCC_VENDOR(broadcast, id) ((id) + ((broadcast) ? 0x61U : 0xE0U))
180
182#define I3C_CCC_SETDASA 0x87U
183
185#define I3C_CCC_SETNEWDA 0x88U
186
188#define I3C_CCC_GETMWL 0x8BU
189
191#define I3C_CCC_GETMRL 0x8CU
192
194#define I3C_CCC_GETPID 0x8DU
195
197#define I3C_CCC_GETBCR 0x8EU
198
200#define I3C_CCC_GETDCR 0x8FU
201
203#define I3C_CCC_GETSTATUS 0x90U
204
206#define I3C_CCC_GETACCCR 0x91U
207
209#define I3C_CCC_SETBRGTGT 0x93U
210
212#define I3C_CCC_GETMXDS 0x94U
213
215#define I3C_CCC_GETCAPS 0x95U
216
218#define I3C_CCC_SETROUTE 0x96U
219
221#define I3C_CCC_D2DXFER 0x97U
222
224#define I3C_CCC_GETXTIME 0x99U
225
227#define I3C_CCC_SETGRPA 0x9BU
228
229struct i3c_device_desc;
230
237
240
249
251 size_t data_len;
252
260 size_t num_xfer;
261};
262
267 struct {
272
280
282 size_t data_len;
283
290 size_t num_xfer;
292
293 struct {
303
307};
308
323} __packed;
324
326#define I3C_CCC_ENEC_EVT_ENINTR BIT(0)
327
329#define I3C_CCC_ENEC_EVT_ENCR BIT(1)
330
332#define I3C_CCC_ENEC_EVT_ENHJ BIT(3)
333
334#define I3C_CCC_ENEC_EVT_ALL \
335 (I3C_CCC_ENEC_EVT_ENINTR | I3C_CCC_ENEC_EVT_ENCR | I3C_CCC_ENEC_EVT_ENHJ)
336
338#define I3C_CCC_DISEC_EVT_DISINTR BIT(0)
339
341#define I3C_CCC_DISEC_EVT_DISCR BIT(1)
342
344#define I3C_CCC_DISEC_EVT_DISHJ BIT(3)
345
346#define I3C_CCC_DISEC_EVT_ALL \
347 (I3C_CCC_DISEC_EVT_DISINTR | I3C_CCC_DISEC_EVT_DISCR | I3C_CCC_DISEC_EVT_DISHJ)
348
349/*
350 * Events for both enabling and disabling since
351 * they have the same bits.
352 */
353
355#define I3C_CCC_EVT_INTR BIT(0)
356
358#define I3C_CCC_EVT_CR BIT(1)
359
361#define I3C_CCC_EVT_HJ BIT(3)
362
364#define I3C_CCC_EVT_ALL \
365 (I3C_CCC_EVT_INTR | I3C_CCC_EVT_CR | I3C_CCC_EVT_HJ)
366
378} __packed;
379
391
394} __packed;
395
405
408
411
414};
415
425
426 union {
432
435 };
436
439
442};
443
455
458} __packed;
459
489} __packed;
490
501} __packed;
502
509} __packed;
510
517} __packed;
518
519
526
529};
530
537
540
544
549 struct {
565
566 union {
573
587
590} __packed;
591
593#define I3C_CCC_GETSTATUS_PROTOCOL_ERR BIT(5)
594
596#define I3C_CCC_GETSTATUS_ACTIVITY_MODE_SHIFT 6
597
599#define I3C_CCC_GETSTATUS_ACTIVITY_MODE_MASK \
600 (0x03U << I3C_CCC_GETSTATUS_ACTIVITY_MODE_SHIFT)
601
610#define I3C_CCC_GETSTATUS_ACTIVITY_MODE(status) \
611 (((status) & I3C_CCC_GETSTATUS_ACTIVITY_MODE_MASK) \
612 >> I3C_CCC_GETSTATUS_ACTIVITY_MODE_SHIFT)
613
615#define I3C_CCC_GETSTATUS_NUM_INT_SHIFT 0
616
618#define I3C_CCC_GETSTATUS_NUM_INT_MASK \
619 (0x0FU << I3C_CCC_GETSTATUS_NUM_INT_SHIFT)
620
629#define I3C_CCC_GETSTATUS_NUM_INT(status) \
630 (((status) & I3C_CCC_GETSTATUS_NUM_INT_MASK) \
631 >> I3C_CCC_GETSTATUS_NUM_INT_SHIFT)
632
634#define I3C_CCC_GETSTATUS_PRECR_DEEP_SLEEP_DETECTED BIT(0)
635
637#define I3C_CCC_GETSTATUS_PRECR_HANDOFF_DELAY_NACK BIT(1)
638
650
660} __packed;
661
672
675} __packed;
676
683 struct {
686
690
691 struct {
694
697
705
706 struct {
713
721} __packed;
722
724#define I3C_CCC_GETMXDS_MAX_SDR_FSCL_MAX 0
725
727#define I3C_CCC_GETMXDS_MAX_SDR_FSCL_8MHZ 1
728
730#define I3C_CCC_GETMXDS_MAX_SDR_FSCL_6MHZ 2
731
733#define I3C_CCC_GETMXDS_MAX_SDR_FSCL_4MHZ 3
734
736#define I3C_CCC_GETMXDS_MAX_SDR_FSCL_2MHZ 4
737
739#define I3C_CCC_GETMXDS_TSCO_8NS 0
740
742#define I3C_CCC_GETMXDS_TSCO_9NS 1
743
745#define I3C_CCC_GETMXDS_TSCO_10NS 2
746
748#define I3C_CCC_GETMXDS_TSCO_11NS 3
749
751#define I3C_CCC_GETMXDS_TSCO_12NS 4
752
754#define I3C_CCC_GETMXDS_TSCO_GT_12NS 7
755
757#define I3C_CCC_GETMXDS_MAXWR_DEFINING_BYTE_SUPPORT BIT(3)
758
760#define I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL_SHIFT 0
761
763#define I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL_MASK \
764 (0x07U << I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL_SHIFT)
765
774#define I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL(maxwr) \
775 (((maxwr) & \
776 I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL_MASK) \
777 >> I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL_SHIFT)
778
780#define I3C_CCC_GETMXDS_MAXRD_W2R_PERMITS_STOP_BETWEEN BIT(6)
781
783#define I3C_CCC_GETMXDS_MAXRD_TSCO_SHIFT 3
784
786#define I3C_CCC_GETMXDS_MAXRD_TSCO_MASK \
787 (0x07U << I3C_CCC_GETMXDS_MAXRD_TSCO_SHIFT)
788
797#define I3C_CCC_GETMXDS_MAXRD_TSCO(maxrd) \
798 (((maxrd) & I3C_CCC_GETMXDS_MAXRD_TSCO_MASK) \
799 >> I3C_CCC_GETMXDS_MAXRD_TSCO_SHIFT)
800
802#define I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL_SHIFT 0
803
805#define I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL_MASK \
806 (0x07U << I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL_SHIFT)
807
816#define I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL(maxrd) \
817 (((maxrd) & \
818 I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL_MASK) \
819 >> I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL_SHIFT)
820
822#define I3C_CCC_GETMXDS_CRDHLY1_SET_BUS_ACT_STATE BIT(2)
823
825#define I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE_SHIFT 0
826
828#define I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE_MASK \
829 (0x03U << I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE_SHIFT)
830
839#define I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE(crhdly1) \
840 (((crhdly1) & \
841 I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE_MASK) \
842 >> I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE_SHIFT)
843
850
853};
854
861
864
867
870
873
876};
877
886 union {
895
923
924 union {
931
938
952
966} __packed;
967
969#define I3C_CCC_GETCAPS1_HDR_DDR BIT(0)
970
972#define I3C_CCC_GETCAPS1_HDR_TSP BIT(1)
973
975#define I3C_CCC_GETCAPS1_HDR_TSL BIT(2)
976
978#define I3C_CCC_GETCAPS1_HDR_BT BIT(3)
979
987#define I3C_CCC_GETCAPS1_HDR_MODE(x) BIT(x)
988
990#define I3C_CCC_GETCAPS1_HDR_MODE0 BIT(0)
991
993#define I3C_CCC_GETCAPS1_HDR_MODE1 BIT(1)
994
996#define I3C_CCC_GETCAPS1_HDR_MODE2 BIT(2)
997
999#define I3C_CCC_GETCAPS1_HDR_MODE3 BIT(3)
1000
1002#define I3C_CCC_GETCAPS1_HDR_MODE4 BIT(4)
1003
1005#define I3C_CCC_GETCAPS1_HDR_MODE5 BIT(5)
1006
1008#define I3C_CCC_GETCAPS1_HDR_MODE6 BIT(6)
1009
1011#define I3C_CCC_GETCAPS1_HDR_MODE7 BIT(7)
1012
1014#define I3C_CCC_GETCAPS2_HDRDDR_WRITE_ABORT BIT(6)
1015
1017#define I3C_CCC_GETCAPS2_HDRDDR_ABORT_CRC BIT(7)
1018
1023#define I3C_CCC_GETCAPS2_GRPADDR_CAP_SHIFT 4
1024
1029#define I3C_CCC_GETCAPS2_GRPADDR_CAP_MASK \
1030 (0x03U << I3C_CCC_GETCAPS2_GRPADDR_CAP_SHIFT)
1031
1040#define I3C_CCC_GETCAPS2_GRPADDR_CAP(getcaps2) \
1041 (((getcaps2) & \
1042 I3C_CCC_GETCAPS2_GRPADDR_CAP_MASK) \
1043 >> I3C_CCC_GETCAPS_GRPADDR_CAP_SHIFT)
1044
1049#define I3C_CCC_GETCAPS2_SPEC_VER_SHIFT 0
1050
1055#define I3C_CCC_GETCAPS2_SPEC_VER_MASK \
1056 (0x0FU << I3C_CCC_GETCAPS2_SPEC_VER_SHIFT)
1057
1067#define I3C_CCC_GETCAPS2_SPEC_VER(getcaps2) \
1068 (((getcaps2) & \
1069 I3C_CCC_GETCAPS2_SPEC_VER_MASK) \
1070 >> I3C_CCC_GETCAPS_SPEC_VER_SHIFT)
1071
1076#define I3C_CCC_GETCAPS3_MLANE_SUPPORT BIT(0)
1077
1082#define I3C_CCC_GETCAPS3_D2DXFER_SUPPORT BIT(1)
1083
1088#define I3C_CCC_GETCAPS3_D2DXFER_IBI_CAPABLE BIT(2)
1089
1094#define I3C_CCC_GETCAPS3_GETCAPS_DEFINING_BYTE_SUPPORT BIT(3)
1095
1100#define I3C_CCC_GETCAPS3_GETSTATUS_DEFINING_BYTE_SUPPORT BIT(4)
1101
1106#define I3C_CCC_GETCAPS3_HDRBT_CRC32_SUPPORT BIT(5)
1107
1112#define I3C_CCC_GETCAPS3_IBI_MDR_PENDING_READ_NOTIFICATION BIT(6)
1113
1118#define I3C_CCC_GETCAPS_TESTPAT1 0xA5
1119
1124#define I3C_CCC_GETCAPS_TESTPAT2 0x5A
1125
1130#define I3C_CCC_GETCAPS_TESTPAT3 0xA5
1131
1136#define I3C_CCC_GETCAPS_TESTPAT4 0x5A
1137
1142#define I3C_CCC_GETCAPS_TESTPAT 0xA55AA55A
1143
1148#define I3C_CCC_GETCAPS_CRCAPS1_HJ_SUPPORT BIT(0)
1149
1154#define I3C_CCC_GETCAPS_CRCAPS1_GRP_MANAGEMENT_SUPPORT BIT(1)
1155
1160#define I3C_CCC_GETCAPS_CRCAPS1_ML_SUPPORT BIT(2)
1161
1166#define I3C_CCC_GETCAPS_CRCAPS2_IBI_TIR_SUPPORT BIT(0)
1167
1172#define I3C_CCC_GETCAPS_CRCAPS2_CONTROLLER_PASSBACK BIT(1)
1173
1178#define I3C_CCC_GETCAPS_CRCAPS2_DEEP_SLEEP_CAPABLE BIT(2)
1179
1184#define I3C_CCC_GETCAPS_CRCAPS2_DELAYED_CONTROLLER_HANDOFF BIT(3)
1185
1187#define I3C_CCC_GETCAPS_VTCAP1_VITRUAL_TARGET_TYPE_SHIFT 0
1188
1190#define I3C_CCC_GETCAPS_VTCAP1_VITRUAL_TARGET_TYPE_MASK \
1191 (0x07U << I3C_CCC_GETCAPS_VTCAP1_VITRUAL_TARGET_TYPE_SHIFT)
1192
1201#define I3C_CCC_GETCAPS_VTCAP1_VITRUAL_TARGET_TYPE(vtcap1) \
1202 (((vtcap1) & \
1203 I3C_CCC_GETCAPS_VTCAP1_VITRUAL_TARGET_TYPE_MASK) \
1204 >> I3C_CCC_GETCAPS_VTCAP1_VITRUAL_TARGET_TYPE_SHIFT)
1205
1210#define I3C_CCC_GETCAPS_VTCAP1_SIDE_EFFECTS BIT(4)
1211
1216#define I3C_CCC_GETCAPS_VTCAP1_SHARED_PERIPH_DETECT BIT(5)
1217
1219#define I3C_CCC_GETCAPS_VTCAP2_INTERRUPT_REQUESTS_SHIFT 0
1220
1222#define I3C_CCC_GETCAPS_VTCAP2_INTERRUPT_REQUESTS_MASK \
1223 (0x03U << I3C_CCC_GETCAPS_VTCAP2_INTERRUPT_REQUESTS_SHIFT)
1224
1233#define I3C_CCC_GETCAPS_VTCAP2_INTERRUPT_REQUESTS(vtcap2) \
1234 (((vtcap2) & \
1235 I3C_CCC_GETCAPS_VTCAP2_INTERRUPT_REQUESTS_MASK) \
1236 >> I3C_CCC_GETCAPS_VTCAP2_INTERRUPT_REQUESTS_SHIFT)
1237
1242#define I3C_CCC_GETCAPS_VTCAP2_ADDRESS_REMAPPING BIT(2)
1243
1245#define I3C_CCC_GETCAPS_VTCAP2_BUS_CONTEXT_AND_COND_SHIFT 3
1246
1248#define I3C_CCC_GETCAPS_VTCAP2_BUS_CONTEXT_AND_COND_MASK \
1249 (0x03U << I3C_CCC_GETCAPS_VTCAP2_BUS_CONTEXT_AND_COND_SHIFT)
1250
1259#define I3C_CCC_GETCAPS_VTCAP2_BUS_CONTEXT_AND_COND(vtcap2) \
1260 (((vtcap2) & \
1261 I3C_CCC_GETCAPS_VTCAP2_BUS_CONTEXT_AND_COND_MASK) \
1262 >> I3C_CCC_GETCAPS_VTCAP2_BUS_CONTEXT_AND_COND_SHIFT)
1263
1270
1273
1276
1279
1282};
1283
1294static inline bool i3c_ccc_is_payload_broadcast(const struct i3c_ccc_payload *payload)
1295{
1296 return (payload->ccc.id <= I3C_CCC_BROADCAST_MAX_ID);
1297}
1298
1311 struct i3c_ccc_getbcr *bcr);
1312
1325 struct i3c_ccc_getdcr *dcr);
1326
1339 struct i3c_ccc_getpid *pid);
1340
1352int i3c_ccc_do_rstact_all(const struct device *controller,
1353 enum i3c_ccc_rstact_defining_byte action);
1354
1364int i3c_ccc_do_rstdaa_all(const struct device *controller);
1365
1379int i3c_ccc_do_setdasa(const struct i3c_device_desc *target);
1380
1394int i3c_ccc_do_setnewda(const struct i3c_device_desc *target,
1395 struct i3c_ccc_address new_da);
1396
1409int i3c_ccc_do_events_all_set(const struct device *controller,
1410 bool enable, struct i3c_ccc_events *events);
1411
1425 bool enable, struct i3c_ccc_events *events);
1426
1438int i3c_ccc_do_setmwl_all(const struct device *controller,
1439 const struct i3c_ccc_mwl *mwl);
1440
1452int i3c_ccc_do_setmwl(const struct i3c_device_desc *target,
1453 const struct i3c_ccc_mwl *mwl);
1454
1466int i3c_ccc_do_getmwl(const struct i3c_device_desc *target,
1467 struct i3c_ccc_mwl *mwl);
1468
1482int i3c_ccc_do_setmrl_all(const struct device *controller,
1483 const struct i3c_ccc_mrl *mrl,
1484 bool has_ibi_size);
1485
1500int i3c_ccc_do_setmrl(const struct i3c_device_desc *target,
1501 const struct i3c_ccc_mrl *mrl);
1502
1517int i3c_ccc_do_getmrl(const struct i3c_device_desc *target,
1518 struct i3c_ccc_mrl *mrl);
1519
1536int i3c_ccc_do_getstatus(const struct i3c_device_desc *target,
1537 union i3c_ccc_getstatus *status,
1538 enum i3c_ccc_getstatus_fmt fmt,
1539 enum i3c_ccc_getstatus_defbyte defbyte);
1540
1552static inline int i3c_ccc_do_getstatus_fmt1(const struct i3c_device_desc *target,
1553 union i3c_ccc_getstatus *status)
1554{
1555 return i3c_ccc_do_getstatus(target, status,
1558}
1559
1572static inline int i3c_ccc_do_getstatus_fmt2(const struct i3c_device_desc *target,
1573 union i3c_ccc_getstatus *status,
1574 enum i3c_ccc_getstatus_defbyte defbyte)
1575{
1576 return i3c_ccc_do_getstatus(target, status,
1577 GETSTATUS_FORMAT_2, defbyte);
1578}
1579
1596int i3c_ccc_do_getcaps(const struct i3c_device_desc *target,
1597 union i3c_ccc_getcaps *caps,
1598 enum i3c_ccc_getcaps_fmt fmt,
1599 enum i3c_ccc_getcaps_defbyte defbyte);
1600
1612static inline int i3c_ccc_do_getcaps_fmt1(const struct i3c_device_desc *target,
1613 union i3c_ccc_getcaps *caps)
1614{
1615 return i3c_ccc_do_getcaps(target, caps,
1618}
1619
1632static inline int i3c_ccc_do_getcaps_fmt2(const struct i3c_device_desc *target,
1633 union i3c_ccc_getcaps *caps,
1634 enum i3c_ccc_getcaps_defbyte defbyte)
1635{
1636 return i3c_ccc_do_getcaps(target, caps,
1637 GETCAPS_FORMAT_2, defbyte);
1638}
1639
1640#ifdef __cplusplus
1641}
1642#endif
1643
1648#endif /* ZEPHYR_INCLUDE_DRIVERS_I3C_CCC_H_ */
i3c_ccc_getstatus_defbyte
Defining byte values for GETSTATUS Format 2.
Definition: ccc.h:534
static int i3c_ccc_do_getstatus_fmt1(const struct i3c_device_desc *target, union i3c_ccc_getstatus *status)
Single target GETSTATUS to Get Target Status (Format 1).
Definition: ccc.h:1552
int i3c_ccc_do_setmrl_all(const struct device *controller, const struct i3c_ccc_mrl *mrl, bool has_ibi_size)
Broadcast SETMRL to Set Maximum Read Length.
int i3c_ccc_do_rstact_all(const struct device *controller, enum i3c_ccc_rstact_defining_byte action)
Broadcast RSTACT to reset I3C Peripheral.
static int i3c_ccc_do_getstatus_fmt2(const struct i3c_device_desc *target, union i3c_ccc_getstatus *status, enum i3c_ccc_getstatus_defbyte defbyte)
Single target GETSTATUS to Get Target Status (Format 2).
Definition: ccc.h:1572
int i3c_ccc_do_getstatus(const struct i3c_device_desc *target, union i3c_ccc_getstatus *status, enum i3c_ccc_getstatus_fmt fmt, enum i3c_ccc_getstatus_defbyte defbyte)
Single target GETSTATUS to Get Target Status.
i3c_ccc_rstact_defining_byte
Enum for I3C Reset Action (RSTACT) Defining Byte Values.
Definition: ccc.h:1267
int i3c_ccc_do_setmwl_all(const struct device *controller, const struct i3c_ccc_mwl *mwl)
Broadcast SETMWL to Set Maximum Write Length.
int i3c_ccc_do_setnewda(const struct i3c_device_desc *target, struct i3c_ccc_address new_da)
Set New Dynamic Address for a target.
int i3c_ccc_do_setmrl(const struct i3c_device_desc *target, const struct i3c_ccc_mrl *mrl)
Single target SETMRL to Set Maximum Read Length.
i3c_ccc_getstatus_fmt
Indicate which format of GETSTATUS to use.
Definition: ccc.h:523
int i3c_ccc_do_getbcr(struct i3c_device_desc *target, struct i3c_ccc_getbcr *bcr)
Get BCR from a target.
int i3c_ccc_do_getdcr(struct i3c_device_desc *target, struct i3c_ccc_getdcr *dcr)
Get DCR from a target.
int i3c_ccc_do_getpid(struct i3c_device_desc *target, struct i3c_ccc_getpid *pid)
Get PID from a target.
int i3c_ccc_do_getcaps(const struct i3c_device_desc *target, union i3c_ccc_getcaps *caps, enum i3c_ccc_getcaps_fmt fmt, enum i3c_ccc_getcaps_defbyte defbyte)
Single target GETCAPS to Get Target Status.
i3c_ccc_getcaps_fmt
Indicate which format of GETCAPS to use.
Definition: ccc.h:847
static int i3c_ccc_do_getcaps_fmt2(const struct i3c_device_desc *target, union i3c_ccc_getcaps *caps, enum i3c_ccc_getcaps_defbyte defbyte)
Single target GETCAPS to Get Capabilities (Format 2).
Definition: ccc.h:1632
static bool i3c_ccc_is_payload_broadcast(const struct i3c_ccc_payload *payload)
Test if I3C CCC payload is for broadcast.
Definition: ccc.h:1294
int i3c_ccc_do_rstdaa_all(const struct device *controller)
Broadcast RSTDAA to reset dynamic addresses for all targets.
int i3c_ccc_do_setmwl(const struct i3c_device_desc *target, const struct i3c_ccc_mwl *mwl)
Single target SETMWL to Set Maximum Write Length.
int i3c_ccc_do_getmrl(const struct i3c_device_desc *target, struct i3c_ccc_mrl *mrl)
Single target GETMRL to Get Maximum Read Length.
i3c_ccc_getcaps_defbyte
Enum for I3C Get Capabilities (GETCAPS) Format 2 Defining Byte Values.
Definition: ccc.h:858
int i3c_ccc_do_setdasa(const struct i3c_device_desc *target)
Set Dynamic Address from Static Address for a target.
static int i3c_ccc_do_getcaps_fmt1(const struct i3c_device_desc *target, union i3c_ccc_getcaps *caps)
Single target GETCAPS to Get Capabilities (Format 1).
Definition: ccc.h:1612
int i3c_ccc_do_getmwl(const struct i3c_device_desc *target, struct i3c_ccc_mwl *mwl)
Single target GETMWL to Get Maximum Write Length.
int i3c_ccc_do_events_all_set(const struct device *controller, bool enable, struct i3c_ccc_events *events)
Broadcast ENEC/DISEC to enable/disable target events.
int i3c_ccc_do_events_set(struct i3c_device_desc *target, bool enable, struct i3c_ccc_events *events)
Direct CCC ENEC/DISEC to enable/disable target events.
#define I3C_CCC_BROADCAST_MAX_ID
Maximum CCC ID for broadcast.
Definition: ccc.h:28
@ GETSTATUS_FORMAT_2_PRECR
PRECR - Alternate status format describing Controller-capable device.
Definition: ccc.h:539
@ GETSTATUS_FORMAT_2_INVALID
Invalid defining byte.
Definition: ccc.h:542
@ GETSTATUS_FORMAT_2_TGTSTAT
Target status.
Definition: ccc.h:536
@ I3C_CCC_RSTACT_PERIPHERAL_ONLY
Reset the I3C Peripheral Only.
Definition: ccc.h:1272
@ I3C_CCC_RSTACT_DEBUG_NETWORK_ADAPTER
Debug Network Adapter Reset.
Definition: ccc.h:1278
@ I3C_CCC_RSTACT_NO_RESET
No Reset on Target Reset Pattern.
Definition: ccc.h:1269
@ I3C_CCC_RSTACT_VIRTUAL_TARGET_DETECT
Virtual Target Detect.
Definition: ccc.h:1281
@ I3C_CCC_RSTACT_RESET_WHOLE_TARGET
Reset the Whole Target.
Definition: ccc.h:1275
@ GETSTATUS_FORMAT_2
GETSTATUS Format 2.
Definition: ccc.h:528
@ GETSTATUS_FORMAT_1
GETSTATUS Format 1.
Definition: ccc.h:525
@ GETCAPS_FORMAT_1
GETCAPS Format 1.
Definition: ccc.h:849
@ GETCAPS_FORMAT_2
GETCAPS Format 2.
Definition: ccc.h:852
@ GETCAPS_FORMAT_2_CRCAPS
Controller handoff capabilities and features.
Definition: ccc.h:866
@ GETCAPS_FORMAT_2_INVALID
Invalid defining byte.
Definition: ccc.h:875
@ GETCAPS_FORMAT_2_TGTCAPS
Standard Target capabilities and features.
Definition: ccc.h:860
@ GETCAPS_FORMAT_2_DBGCAPS
Debug-capable Device capabilities and features.
Definition: ccc.h:872
@ GETCAPS_FORMAT_2_VTCAPS
Virtual Target capabilities and features.
Definition: ccc.h:869
@ GETCAPS_FORMAT_2_TESTPAT
Fixed 32b test pattern.
Definition: ccc.h:863
__UINT32_TYPE__ uint32_t
Definition: stdint.h:90
__UINT8_TYPE__ uint8_t
Definition: stdint.h:88
__UINT16_TYPE__ uint16_t
Definition: stdint.h:89
Runtime device structure (in ROM) per driver instance.
Definition: device.h:399
Payload for a single device address.
Definition: ccc.h:473
uint8_t addr
Definition: ccc.h:488
The active controller part of payload for DEFTGTS CCC.
Definition: ccc.h:402
uint8_t addr
Dynamic Address of Active Controller.
Definition: ccc.h:404
uint8_t dcr
Device Characteristic Register of Active Controller.
Definition: ccc.h:407
uint8_t static_addr
Static Address of Active Controller.
Definition: ccc.h:413
uint8_t bcr
Bus Characteristic Register of Active Controller.
Definition: ccc.h:410
The target device part of payload for DEFTGTS CCC.
Definition: ccc.h:422
uint8_t dcr
Device Characteristic Register of a I3C target device or a group.
Definition: ccc.h:431
uint8_t addr
Dynamic Address of a target device, or a group address.
Definition: ccc.h:424
uint8_t static_addr
Static Address of a target device or a group.
Definition: ccc.h:441
uint8_t bcr
Bus Characteristic Register of a target device or a group.
Definition: ccc.h:438
uint8_t lvr
Legacy Virtual Register for legacy I2C device.
Definition: ccc.h:434
Payload for DEFTGTS CCC (Define List of Targets).
Definition: ccc.h:452
struct i3c_ccc_deftgts_active_controller active_controller
Data describing the active controller.
Definition: ccc.h:454
struct i3c_ccc_deftgts_target targets[]
Data describing the target(s) on the bus.
Definition: ccc.h:457
Payload for ENEC/DISEC CCC (Target Events Command).
Definition: ccc.h:312
uint8_t events
Event byte:
Definition: ccc.h:322
Payload for GETBCR CCC (Get Bus Characteristics Register).
Definition: ccc.h:506
uint8_t bcr
Bus Characteristics Register.
Definition: ccc.h:508
Payload for GETDCR CCC (Get Device Characteristics Register).
Definition: ccc.h:514
uint8_t dcr
Device Characteristics Register.
Definition: ccc.h:516
Payload for GETPID CCC (Get Provisioned ID).
Definition: ccc.h:494
uint8_t pid[6]
48-bit Provisioned ID.
Definition: ccc.h:500
Payload for SETMRL/GETMRL CCC (Set/Get Maximum Read Length).
Definition: ccc.h:388
uint16_t len
Maximum Read Length.
Definition: ccc.h:390
uint8_t ibi_len
Optional IBI Payload Size.
Definition: ccc.h:393
Payload for SETMWL/GETMWL CCC (Set/Get Maximum Write Length).
Definition: ccc.h:375
uint16_t len
Maximum Write Length.
Definition: ccc.h:377
Payload structure for one CCC transaction.
Definition: ccc.h:266
struct i3c_ccc_payload::@172 ccc
struct i3c_ccc_payload::@173 targets
struct i3c_ccc_target_payload * payloads
Array of struct i3c_ccc_target_payload.
Definition: ccc.h:302
size_t num_xfer
Total number of bytes transferred.
Definition: ccc.h:290
uint8_t * data
Pointer to byte array of data for this CCC.
Definition: ccc.h:279
uint8_t id
The CCC ID (I3C_CCC_*).
Definition: ccc.h:271
size_t num_targets
Number of targets.
Definition: ccc.h:305
size_t data_len
Length in bytes for optional data array.
Definition: ccc.h:282
One Bridged Target for SETBRGTGT payload.
Definition: ccc.h:642
uint16_t id
16-bit ID for the bridged target.
Definition: ccc.h:659
uint8_t addr
Dynamic address of the bridged target.
Definition: ccc.h:649
Payload for SETBRGTGT CCC (Set Bridge Targets).
Definition: ccc.h:669
uint8_t count
Number of bridged targets.
Definition: ccc.h:671
struct i3c_ccc_setbrgtgt_tgt targets[]
Array of bridged targets.
Definition: ccc.h:674
Payload structure for Direct CCC to one target.
Definition: ccc.h:234
uint8_t addr
Target address.
Definition: ccc.h:236
size_t data_len
Length in bytes for data.
Definition: ccc.h:251
uint8_t rnw
0 for Write, 1 for Read
Definition: ccc.h:239
uint8_t * data
Definition: ccc.h:248
size_t num_xfer
Total number of bytes transferred.
Definition: ccc.h:260
Structure describing a I3C target device.
Definition: i3c.h:913
Macros to abstract toolchain specific capabilities.
Payload for GETCAPS CCC (Get Optional Feature Capabilities).
Definition: ccc.h:885
union i3c_ccc_getcaps::@181 fmt1
union i3c_ccc_getcaps::@182 fmt2
uint8_t crcaps[2]
Defining Byte 0x91: CRCAPS Byte 1 CRCAPS1.
Definition: ccc.h:951
uint8_t tgtcaps[4]
Defining Byte 0x00: TGTCAPS.
Definition: ccc.h:930
uint8_t getcaps[4]
I3C v1.1+ Device Capabilities Byte 1 GETCAPS1.
Definition: ccc.h:921
uint8_t gethdrcap
I3C v1.0 HDR Capabilities.
Definition: ccc.h:894
uint8_t vtcaps[2]
Defining Byte 0x93: VTCAPS Byte 1 VTCAPS1.
Definition: ccc.h:964
uint32_t testpat
Defining Byte 0x5A: TESTPAT.
Definition: ccc.h:937
Payload for GETMXDS CCC (Get Max Data Speed).
Definition: ccc.h:682
struct i3c_ccc_getmxds::@180 fmt3
uint8_t wrrdturn
Defining Byte 0x00: WRRDTURN.
Definition: ccc.h:712
uint8_t maxrdturn[3]
Maximum Read Turnaround Time in microsecond.
Definition: ccc.h:703
uint8_t maxrd
maxRd
Definition: ccc.h:688
struct i3c_ccc_getmxds::@179 fmt2
uint8_t maxwr
maxWr
Definition: ccc.h:685
uint8_t crhdly1
Defining Byte 0x91: CRHDLY.
Definition: ccc.h:719
struct i3c_ccc_getmxds::@178 fmt1
Payload for GETSTATUS CCC (Get Device Status).
Definition: ccc.h:548
uint16_t precr
Defining Byte 0x91: PRECR.
Definition: ccc.h:586
uint16_t tgtstat
Defining Byte 0x00: TGTSTAT.
Definition: ccc.h:572
struct i3c_ccc_getstatus::@176 fmt1
uint16_t status
Device Status.
Definition: ccc.h:563
uint16_t raw_u16
Definition: ccc.h:588
union i3c_ccc_getstatus::@177 fmt2
Misc utilities.