st,stm32-qspi¶
Vendor: STMicroelectronics
Description¶
These nodes are “qspi” bus nodes.
STM32 QSPI device representation. A stm32 quadspi node would typically
looks to this:
&quadspi {
pinctrl-0 = <&quadspi_clk_pe10 &quadspi_ncs_pe11
&quadspi_bk1_io0_pe12 &quadspi_bk1_io1_pe13
&quadspi_bk1_io2_pe14 &quadspi_bk1_io3_pe15>;
dmas = <&dma1 5 5 0x0000 0x03>;
dma-names = "tx_rx";
status = "okay";
};
Properties¶
Properties not inherited from the base binding file.
Name |
Type |
Details |
|---|---|---|
|
|
This property is required. |
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “st,stm32-qspi” compatible.
Name |
Type |
Details |
|---|---|---|
|
|
register space
This property is required. See Important properties for more information. |
|
|
interrupts for device
This property is required. See Important properties for more information. |
|
|
Optional DMA channel specifier. If DMA should be used, specifier should
hold a phandle reference to the dma controller, the channel number,
the slot number, channel configuration and finally features.
For example dmas for TX/RX on QSPI
dmas = <&dma1 5 5 0x0000 0x03>;
|
|
|
DMA channel name. If DMA should be used, expected value is "tx_rx".
For example
dma-names = "tx_rx";
|
|
|
indicates the operational status of a device
Legal values: See Important properties for more information. |
|
|
compatible strings
This property is required. See Important properties for more information. |
|
|
name of each register space
|
|
|
extended interrupt specifier for device
|
|
|
name of each interrupt
|
|
|
phandle to interrupt controller node
|
|
|
Human readable string describing the device (used as device_get_binding() argument)
See Important properties for more information. |
|
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Clock gate information
|
|
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name of each clock
|
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number of address cells in reg property
|
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number of size cells in reg property
|
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IO channels specifiers
|
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Provided names of IO channel specifiers
|