st,stm32-qspi-nor (on qspi bus)¶
Vendor: STMicroelectronics
Description¶
STM32 QSPI Flash controller supporting the JEDEC CFI interface
Representation of a serial flash on a quadspi bus:
mx25r6435f: qspi-nor-flash@0 {
compatible = "st,stm32-qspi-nor";
label = "MX25R6435F";
reg = <0>;
qspi-max-frequency = <80000000>;
size = <0x4000000>;
status = "okay";
};
Properties¶
Properties not inherited from the base binding file.
Name |
Type |
Details |
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Maximum clock frequency of device's QSPI interface in Hz
This property is required. |
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Flash Memory size in bits
This property is required. |
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JEDEC ID as manufacturer ID, memory type, memory density
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Contains the 32-bit words in little-endian byte order from the
JESD216 Serial Flash Discoverable Parameters Basic Flash
Parameters table. This provides flash-specific configuration
information in cases were runtime retrieval of SFDP data
is not desired.
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Not used after Zephyr 2.3.0
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Quad Enable Requirements value from JESD216 BFP DW15.
Use NONE if the device detects 1-1-4 and 1-4-4 modes by the
instruction. Use S1B6 if QE is bit 6 of the first status register
byte, and can be configured by reading then writing one byte with
RDSR and WRSR. For other fields see the specification.
Legal values: |
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “st,stm32-qspi-nor” compatible.
Name |
Type |
Details |
---|---|---|
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register space
This property is required. See Important properties for more information. |
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Human readable string describing the device (used as device_get_binding() argument)
This property is required. See Important properties for more information. |
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indicates the operational status of a device
Legal values: See Important properties for more information. |
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compatible strings
This property is required. See Important properties for more information. |
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name of each register space
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interrupts for device
See Important properties for more information. |
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extended interrupt specifier for device
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name of each interrupt
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phandle to interrupt controller node
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Clock gate information
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name of each clock
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number of address cells in reg property
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number of size cells in reg property
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DMA channels specifiers
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Provided names of DMA channel specifiers
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IO channels specifiers
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Provided names of IO channel specifiers
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