st,stm32-fmc¶
Vendor: STMicroelectronics
Description¶
STM32 Flexible Memory Controller (FMC).
The FMC allows to interface with static-memory mapped external devices such as
SRAM, NOR Flash, NAND Flash, SDRAM...
All external memories share the addresses, data and control signals with the
controller. Each external device is accessed by means of a unique chip select.
The FMC performs only one access at a time to an external device.
The flexible memory controller includes three memory controllers:
- NOR/PSRAM memory controller
- NAND memory controller (some devices also support PC Card)
- Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller
Each memory controller is defined below the FMC DeviceTree node and is managed
by a separate Zephyr device. However, because signals are shared the FMC
device handles the signals and the peripheral clocks. FMC can be enabled
in your board DeviceTree file like this:
&fmc {
status = "okay";
pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1 &fmc_nbl2_pi4...>;
};
Properties¶
Properties not inherited from the base binding file.
Name |
Type |
Details |
---|---|---|
|
|
GPIO pin configuration for FMC signals. We expect that the phandles
will reference pinctrl nodes, e.g.
pinctrl-0 = <&fmc_a0_pf0 &fmc_a1_pf1...>;
|
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “st,stm32-fmc” compatible.
Name |
Type |
Details |
---|---|---|
|
|
register space
This property is required. See Important properties for more information. |
|
|
Human readable string describing the device (used as device_get_binding() argument)
This property is required. See Important properties for more information. |
|
|
Clock gate information
This property is required. |
|
|
indicates the operational status of a device
Legal values: See Important properties for more information. |
|
|
compatible strings
This property is required. See Important properties for more information. |
|
|
name of each register space
|
|
|
interrupts for device
See Important properties for more information. |
|
|
extended interrupt specifier for device
|
|
|
name of each interrupt
|
|
|
phandle to interrupt controller node
|
|
|
name of each clock
|
|
|
number of address cells in reg property
|
|
|
number of size cells in reg property
|
|
|
DMA channels specifiers
|
|
|
Provided names of DMA channel specifiers
|
|
|
IO channels specifiers
|
|
|
Provided names of IO channel specifiers
|