nxp,kinetis-dspi

Vendor: NXP Semiconductors

Description

These nodes are “spi” bus nodes.

NXP Kinetis DSPI controller

Properties

Properties not inherited from the base binding file.

Name

Type

Details

pcs-sck-delay

int

 
Delay in nanoseconds from the chip select assert to the first clock
edge. If not set, the minimum supported delay is used.

sck-pcs-delay

int

 
Delay in nanoseconds from the last clock edge to the chip select
deassert. If not set, the minimum supported delay is used.

transfer-delay

int

 
Delay in nanoseconds from the chip select deassert to the next chip
select assert. If not set, the minimum supported delay is used.

clock-frequency

int

 
Clock frequency the SPI peripheral is being driven at, in Hz.

cs-gpios

phandle-array

 
An array of chip select GPIOs to use. Each element
in the array specifies a GPIO. The index in the array
corresponds to the child node that the CS gpio controls.

Example:

  spi@... {
          cs-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>,
                        <&gpio1 10 GPIO_ACTIVE_LOW>,
                        ...;

          spi-device@0 {
                  reg = <0>;
                  ...
          };
          spi-device@1 {
                  reg = <1>;
                  ...
          };
          ...
  };

The child node "spi-device@0" specifies a SPI device with
chip select controller gpio0, pin 23, and devicetree
GPIO flags GPIO_ACTIVE_LOW. Similarly, "spi-device@1" has CS GPIO
controller gpio1, pin 10, and flags GPIO_ACTIVE_LOW. Additional
devices can be configured in the same way.

If unsure about the flags cell, GPIO_ACTIVE_LOW is generally a safe
choice for a typical "CSn" pin. GPIO_ACTIVE_HIGH may be used if
intervening hardware inverts the signal to the peripheral device or
the line itself is active high.

If this property is not defined, no chip select GPIOs are set.
SPI controllers with dedicated CS pins do not need to define
the cs-gpios property.