intel,apollo-lake-gpio¶
Vendor: Intel Corporation
Description¶
Apollo Lake GPIO Map
Map from Apollo Lake GPIO to component GPIO driver instances.
The Apollo Lake GPIO architecture provides four controllers each of
which has more than 32 pins. To be supported on Zephyr these pins
must be mapped to sub-devices that have no more than 32 pins each.
This compatible is used to map the full controller to its
subdevices.
The NORTH controller supports 78 pins.
The NORTHWEST controller supports 77 pins.
The WEST controller supports 47 pins.
The SOUTHWEST controller supports 43 pins.
Properties¶
Properties not inherited from the base binding file.
Name |
Type |
Details |
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This property is required. |
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Number of items to expect in a GPIO specifier
This property is required. |
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “intel,apollo-lake-gpio” compatible.
Name |
Type |
Details |
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indicates the operational status of a device
Legal values: See Important properties for more information. |
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compatible strings
This property is required. See Important properties for more information. |
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register space
See Important properties for more information. |
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name of each register space
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interrupts for device
See Important properties for more information. |
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extended interrupt specifier for device
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name of each interrupt
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phandle to interrupt controller node
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Human readable string describing the device (used as device_get_binding() argument)
See Important properties for more information. |
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Clock gate information
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name of each clock
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number of address cells in reg property
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number of size cells in reg property
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DMA channels specifiers
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Provided names of DMA channel specifiers
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IO channels specifiers
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Provided names of IO channel specifiers
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