cadence,tensilica-xtensa-lx6¶

Description¶

Cadence Tensilica Xtensa LX6 CPU

Properties¶

Properties not inherited from the base binding file.

Name	Type	Details
`clock-source`	`int`	cpu clock source
`clock-frequency`	`int`	Clock frequency in Hz
`pm-states`	`phandles`	List of power management states supported by this cpu
`i-cache-line-size`	`int`	i-cache line size
`d-cache-line-size`	`int`	d-cache line size

Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “cadence,tensilica-xtensa-lx6” compatible.

Name	Type	Details
`status`	`string`	indicates the operational status of a device Legal values: `'ok'`, `'okay'`, `'disabled'`, `'reserved'`, `'fail'`, `'fail-sss'` See Important properties for more information.
`compatible`	`string-array`	compatible strings This property is required. See Important properties for more information.
`reg`	`array`	register space See Important properties for more information.
`reg-names`	`string-array`	name of each register space
`interrupts`	`array`	interrupts for device See Important properties for more information.
`interrupts-extended`	`compound`	extended interrupt specifier for device
`interrupt-names`	`string-array`	name of each interrupt
`interrupt-parent`	`phandle`	phandle to interrupt controller node
`label`	`string`	Human readable string describing the device (used as device_get_binding() argument) See Important properties for more information.
`clocks`	`phandle-array`	Clock gate information
`clock-names`	`string-array`	name of each clock
`#address-cells`	`int`	number of address cells in reg property
`#size-cells`	`int`	number of size cells in reg property
`dmas`	`phandle-array`	DMA channels specifiers
`dma-names`	`string-array`	Provided names of DMA channel specifiers
`io-channels`	`phandle-array`	IO channels specifiers
`io-channel-names`	`string-array`	Provided names of IO channel specifiers