-
CONFIG_SOC_ATMEL_SAMV71_PLLA_DIVA
¶
PLL DIVA
Type: int
Help¶
This is the divider DIVA used by the PLL. The processor clock is (MAINCK * (MULA + 1) / DIVA).
Board config file can override this settings for a particular board.
Setting DIVA=0 would disable PLL at boot, this is currently not supported.
With default of MULA == 24, and DIVA == 1, PLL is running at 25 times the main clock frequency.
Direct dependencies¶
SOC_SERIES_SAMV71
&& SOC_FAMILY_SAM
(Includes any dependencies from ifs and menus.)
Default¶
1
Kconfig definition¶
At <Zephyr>/soc/arm/atmel_sam/samv71/Kconfig.soc:134
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:28
→ <Zephyr>/soc/Kconfig:11
→ <BuildDir>/Kconfig/Kconfig.soc.arch:2
→ <Zephyr>/soc/arm/atmel_sam/Kconfig:17
Menu path: (Top) → Hardware Configuration
config SOC_ATMEL_SAMV71_PLLA_DIVA int "PLL DIVA" range 1 255 default 1 depends onSOC_SERIES_SAMV71
&&SOC_FAMILY_SAM
help This is the divider DIVA used by the PLL. The processor clock is (MAINCK * (MULA + 1) / DIVA). Board config file can override this settings for a particular board. Setting DIVA=0 would disable PLL at boot, this is currently not supported. With default of MULA == 24, and DIVA == 1, PLL is running at 25 times the main clock frequency.
(The ‘depends on’ condition includes propagated dependencies from ifs and menus.)