Help¶

PLL3 Q Output divisor, allowed values: 1-128.

Direct dependencies¶

CLOCK_STM32_PLL3_Q_ENABLE && CLOCK_STM32_PLL3_ENABLE && SOC_SERIES_STM32H7X && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL

(Includes any dependencies from ifs and menus.)

Default¶

2

Kconfig definition¶

At <Zephyr>/drivers/clock_control/Kconfig.stm32h7:148

Included via <Zephyr>/Kconfig:8 → <Zephyr>/Kconfig.zephyr:32 → <Zephyr>/drivers/Kconfig:54 → <Zephyr>/drivers/clock_control/Kconfig:25 → <Zephyr>/drivers/clock_control/Kconfig.stm32:133

Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control → Enable PLL3 → Enable PLL3 Q output

config CLOCK_STM32_PLL3_Q_DIVISOR
    int "PLL3 Q Divisor"
    range 1 128
    default 2
    depends on CLOCK_STM32_PLL3_Q_ENABLE && CLOCK_STM32_PLL3_ENABLE && SOC_SERIES_STM32H7X && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL
    help
      PLL3 Q Output divisor, allowed values: 1-128.

(The ‘depends on’ condition includes propagated dependencies from ifs and menus.)