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CONFIG_SOC_OPENISA_RV32M1_RISCV32
¶
OpenISA RV32M1 RISC-V cores
Type: bool
Help¶
Enable support for OpenISA RV32M1 RISC-V processors. Choose this option to target the RI5CY or ZERO-RISCY core. This option should not be used to target either Arm core.
Direct dependencies¶
<choice: SoC/CPU/Configuration Selection>
(Includes any dependencies from ifs and menus.)
Symbols selected by this symbol¶
Kconfig definition¶
At <Zephyr>/soc/riscv/openisa_rv32m1/Kconfig.soc:4
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:28
→ <Zephyr>/soc/Kconfig:6
→ <BuildDir>/Kconfig/Kconfig.soc:1
Menu path: (Top) → SoC/CPU/Configuration Selection
config SOC_OPENISA_RV32M1_RISCV32 bool "OpenISA RV32M1 RISC-V cores" selectRISCV
selectXIP
selectHAS_RV32M1_LPUART
selectHAS_RV32M1_LPI2C
selectHAS_RV32M1_LPSPI
selectHAS_RV32M1_TPM
selectATOMIC_OPERATIONS_C
selectVEGA_SDK_HAL
selectRISCV_SOC_INTERRUPT_INIT
selectCLOCK_CONTROL
selectHAS_RV32M1_FTFX
selectHAS_FLASH_LOAD_OFFSET
depends on <choice: SoC/CPU/Configuration Selection> help Enable support for OpenISA RV32M1 RISC-V processors. Choose this option to target the RI5CY or ZERO-RISCY core. This option should not be used to target either Arm core.
(The ‘depends on’ condition includes propagated dependencies from ifs and menus.)