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CONFIG_2ND_LVL_ISR_TBL_OFFSET
¶
Offset in _sw_isr_table for level 2 interrupts
Type: int
Help¶
This is the offset in _sw_isr_table, the generated ISR handler table, where storage for 2nd level interrupt ISRs begins. This is typically allocated after ISRs for level 1 interrupts.
Direct dependencies¶
BOARD_UP_SQUARED_ADSP
|| BOARD_INTEL_ADSP_CAVS18
|| BOARD_INTEL_ADSP_CAVS20
|| BOARD_INTEL_ADSP_CAVS25
|| BOARD_INTEL_S1000_CRB
|| (MULTI_LEVEL_INTERRUPTS
&& SOC_OPENISA_RV32M1_RISCV32
) || SOC_SERIES_RISCV32_MIV
|| SOC_SERIES_RISCV_SIFIVE_FREEDOM
|| 2ND_LEVEL_INTERRUPTS
(Includes any dependencies from ifs and menus.)
Defaults¶
21
21
21
21
21
32
12
12
0
Kconfig definitions¶
At <Zephyr>/boards/xtensa/intel_adsp_cavs15/Kconfig.defconfig:32
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:24
Menu path: (Top)
config 2ND_LVL_ISR_TBL_OFFSET
int
default 21
depends on BOARD_UP_SQUARED_ADSP
At <Zephyr>/boards/xtensa/intel_adsp_cavs18/Kconfig.defconfig:32
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:24
Menu path: (Top)
config 2ND_LVL_ISR_TBL_OFFSET
int
default 21
depends on BOARD_INTEL_ADSP_CAVS18
At <Zephyr>/boards/xtensa/intel_adsp_cavs20/Kconfig.defconfig:32
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:24
Menu path: (Top)
config 2ND_LVL_ISR_TBL_OFFSET
int
default 21
depends on BOARD_INTEL_ADSP_CAVS20
At <Zephyr>/boards/xtensa/intel_adsp_cavs25/Kconfig.defconfig:32
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:24
Menu path: (Top)
config 2ND_LVL_ISR_TBL_OFFSET
int
default 21
depends on BOARD_INTEL_ADSP_CAVS25
At <Zephyr>/boards/xtensa/intel_s1000_crb/Kconfig.defconfig:38
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:24
Menu path: (Top)
config 2ND_LVL_ISR_TBL_OFFSET
int
default 21
depends on BOARD_INTEL_S1000_CRB
At <Zephyr>/soc/riscv/openisa_rv32m1/Kconfig.defconfig:52
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:25
→ <BuildDir>/Kconfig/Kconfig.soc.defconfig:1
Menu path: (Top)
config 2ND_LVL_ISR_TBL_OFFSET int default 32 depends onMULTI_LEVEL_INTERRUPTS
&&SOC_OPENISA_RV32M1_RISCV32
At <Zephyr>/soc/riscv/riscv-privilege/miv/Kconfig.defconfig.series:20
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:25
→ <BuildDir>/Kconfig/Kconfig.soc.defconfig:1
→ <Zephyr>/soc/riscv/riscv-privilege/Kconfig.defconfig:6
Menu path: (Top)
config 2ND_LVL_ISR_TBL_OFFSET
int
default 12
depends on SOC_SERIES_RISCV32_MIV
At <Zephyr>/soc/riscv/riscv-privilege/sifive-freedom/Kconfig.defconfig.series:20
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:25
→ <BuildDir>/Kconfig/Kconfig.soc.defconfig:1
→ <Zephyr>/soc/riscv/riscv-privilege/Kconfig.defconfig:6
Menu path: (Top)
config 2ND_LVL_ISR_TBL_OFFSET
int
default 12
depends on SOC_SERIES_RISCV_SIFIVE_FREEDOM
At <Zephyr>/drivers/interrupt_controller/Kconfig.multilevel:36
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:32
→ <Zephyr>/drivers/Kconfig:26
→ <Zephyr>/drivers/interrupt_controller/Kconfig:49
Menu path: (Top) → Device Drivers → Interrupt Controllers → Multi-level interrupt support → Second-level interrupt support
config 2ND_LVL_ISR_TBL_OFFSET
int "Offset in _sw_isr_table for level 2 interrupts"
default 0
depends on 2ND_LEVEL_INTERRUPTS
help
This is the offset in _sw_isr_table, the generated ISR handler table,
where storage for 2nd level interrupt ISRs begins. This is
typically allocated after ISRs for level 1 interrupts.
(The ‘depends on’ condition includes propagated dependencies from ifs and menus.)