Zephyr API Documentation  3.6.99
A Scalable Open Source RTOS
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stm32l4_clock.h File Reference

Go to the source code of this file.

Macros

#define STM32_CLOCK_BUS_AHB1   0x048
 Bus clocks.
 
#define STM32_CLOCK_BUS_AHB2   0x04c
 
#define STM32_CLOCK_BUS_AHB3   0x050
 
#define STM32_CLOCK_BUS_APB1   0x058
 
#define STM32_CLOCK_BUS_APB1_2   0x05c
 
#define STM32_CLOCK_BUS_APB2   0x060
 
#define STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1
 
#define STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB2
 
#define STM32_SRC_HSI   (STM32_SRC_LSI + 1)
 Domain clocks.
 
#define STM32_SRC_HSI48   (STM32_SRC_HSI + 1)
 
#define STM32_SRC_MSI   (STM32_SRC_HSI48 + 1)
 
#define STM32_SRC_PCLK   (STM32_SRC_MSI + 1)
 Bus clock.
 
#define STM32_SRC_PLL_P   (STM32_SRC_PCLK + 1)
 PLL clock outputs.
 
#define STM32_SRC_PLL_Q   (STM32_SRC_PLL_P + 1)
 
#define STM32_SRC_PLL_R   (STM32_SRC_PLL_Q + 1)
 
#define STM32_CLOCK_REG_MASK   0xFFU
 
#define STM32_CLOCK_REG_SHIFT   0U
 
#define STM32_CLOCK_SHIFT_MASK   0x1FU
 
#define STM32_CLOCK_SHIFT_SHIFT   8U
 
#define STM32_CLOCK_MASK_MASK   0x7U
 
#define STM32_CLOCK_MASK_SHIFT   13U
 
#define STM32_CLOCK_VAL_MASK   0x7U
 
#define STM32_CLOCK_VAL_SHIFT   16U
 
#define STM32_CLOCK(val, mask, shift, reg)
 STM32 clock configuration bit field.
 
#define CCIPR_REG   0x88
 RCC_CCIPR register offset.
 
#define CCIPR2_REG   0x9C
 
#define BDCR_REG   0x90
 RCC_BDCR register offset.
 
#define USART1_SEL(val)   STM32_CLOCK(val, 3, 0, CCIPR_REG)
 Device domain clocks selection helpers.
 
#define USART2_SEL(val)   STM32_CLOCK(val, 3, 2, CCIPR_REG)
 
#define USART3_SEL(val)   STM32_CLOCK(val, 3, 4, CCIPR_REG)
 
#define UART4_SEL(val)   STM32_CLOCK(val, 3, 6, CCIPR_REG)
 
#define UART5_SEL(val)   STM32_CLOCK(val, 3, 8, CCIPR_REG)
 
#define LPUART1_SEL(val)   STM32_CLOCK(val, 3, 10, CCIPR_REG)
 
#define I2C1_SEL(val)   STM32_CLOCK(val, 3, 12, CCIPR_REG)
 
#define I2C2_SEL(val)   STM32_CLOCK(val, 3, 14, CCIPR_REG)
 
#define I2C3_SEL(val)   STM32_CLOCK(val, 3, 16, CCIPR_REG)
 
#define LPTIM1_SEL(val)   STM32_CLOCK(val, 3, 18, CCIPR_REG)
 
#define LPTIM2_SEL(val)   STM32_CLOCK(val, 3, 20, CCIPR_REG)
 
#define SAI1_SEL(val)   STM32_CLOCK(val, 3, 22, CCIPR_REG)
 
#define SAI2_SEL(val)   STM32_CLOCK(val, 3, 24, CCIPR_REG)
 
#define CLK48_SEL(val)   STM32_CLOCK(val, 3, 26, CCIPR_REG)
 
#define ADC_SEL(val)   STM32_CLOCK(val, 3, 28, CCIPR_REG)
 
#define SWPMI1_SEL(val)   STM32_CLOCK(val, 1, 30, CCIPR_REG)
 
#define DFSDM1_SEL(val)   STM32_CLOCK(val, 1, 31, CCIPR_REG)
 
#define I2C4_SEL(val)   STM32_CLOCK(val, 3, 0, CCIPR2_REG)
 CCIPR2 devices.
 
#define DFSDM_SEL(val)   STM32_CLOCK(val, 1, 2, CCIPR2_REG)
 
#define ADFSDM_SEL(val)   STM32_CLOCK(val, 3, 3, CCIPR2_REG)
 
#define DSI_SEL(val)   STM32_CLOCK(val, 1, 12, CCIPR2_REG)
 
#define SDMMC_SEL(val)   STM32_CLOCK(val, 1, 14, CCIPR2_REG)
 
#define OSPI_SEL(val)   STM32_CLOCK(val, 3, 20, CCIPR2_REG)
 
#define RTC_SEL(val)   STM32_CLOCK(val, 3, 8, BDCR_REG)
 BDCR devices.
 

Macro Definition Documentation

◆ ADC_SEL

#define ADC_SEL (   val)    STM32_CLOCK(val, 3, 28, CCIPR_REG)

◆ ADFSDM_SEL

#define ADFSDM_SEL (   val)    STM32_CLOCK(val, 3, 3, CCIPR2_REG)

◆ BDCR_REG

#define BDCR_REG   0x90

RCC_BDCR register offset.

◆ CCIPR2_REG

#define CCIPR2_REG   0x9C

◆ CCIPR_REG

#define CCIPR_REG   0x88

RCC_CCIPR register offset.

◆ CLK48_SEL

#define CLK48_SEL (   val)    STM32_CLOCK(val, 3, 26, CCIPR_REG)

◆ DFSDM1_SEL

#define DFSDM1_SEL (   val)    STM32_CLOCK(val, 1, 31, CCIPR_REG)

◆ DFSDM_SEL

#define DFSDM_SEL (   val)    STM32_CLOCK(val, 1, 2, CCIPR2_REG)

◆ DSI_SEL

#define DSI_SEL (   val)    STM32_CLOCK(val, 1, 12, CCIPR2_REG)

◆ I2C1_SEL

#define I2C1_SEL (   val)    STM32_CLOCK(val, 3, 12, CCIPR_REG)

◆ I2C2_SEL

#define I2C2_SEL (   val)    STM32_CLOCK(val, 3, 14, CCIPR_REG)

◆ I2C3_SEL

#define I2C3_SEL (   val)    STM32_CLOCK(val, 3, 16, CCIPR_REG)

◆ I2C4_SEL

#define I2C4_SEL (   val)    STM32_CLOCK(val, 3, 0, CCIPR2_REG)

CCIPR2 devices.

◆ LPTIM1_SEL

#define LPTIM1_SEL (   val)    STM32_CLOCK(val, 3, 18, CCIPR_REG)

◆ LPTIM2_SEL

#define LPTIM2_SEL (   val)    STM32_CLOCK(val, 3, 20, CCIPR_REG)

◆ LPUART1_SEL

#define LPUART1_SEL (   val)    STM32_CLOCK(val, 3, 10, CCIPR_REG)

◆ OSPI_SEL

#define OSPI_SEL (   val)    STM32_CLOCK(val, 3, 20, CCIPR2_REG)

◆ RTC_SEL

#define RTC_SEL (   val)    STM32_CLOCK(val, 3, 8, BDCR_REG)

BDCR devices.

◆ SAI1_SEL

#define SAI1_SEL (   val)    STM32_CLOCK(val, 3, 22, CCIPR_REG)

◆ SAI2_SEL

#define SAI2_SEL (   val)    STM32_CLOCK(val, 3, 24, CCIPR_REG)

◆ SDMMC_SEL

#define SDMMC_SEL (   val)    STM32_CLOCK(val, 1, 14, CCIPR2_REG)

◆ STM32_CLOCK

#define STM32_CLOCK (   val,
  mask,
  shift,
  reg 
)
Value:
#define STM32_CLOCK_SHIFT_SHIFT
Definition: stm32l4_clock.h:43
#define STM32_CLOCK_REG_SHIFT
Definition: stm32l4_clock.h:41
#define STM32_CLOCK_REG_MASK
Definition: stm32l4_clock.h:40
#define STM32_CLOCK_MASK_MASK
Definition: stm32l4_clock.h:44
#define STM32_CLOCK_VAL_MASK
Definition: stm32l4_clock.h:46
#define STM32_CLOCK_MASK_SHIFT
Definition: stm32l4_clock.h:45
#define STM32_CLOCK_VAL_SHIFT
Definition: stm32l4_clock.h:47
#define STM32_CLOCK_SHIFT_MASK
Definition: stm32l4_clock.h:42

STM32 clock configuration bit field.

  • reg (1/2/3) [ 0 : 7 ]
  • shift (0..31) [ 8 : 12 ]
  • mask (0x1, 0x3, 0x7) [ 13 : 15 ]
  • val (0..7) [ 16 : 18 ]
Parameters
regRCC_CCIPRx register offset
shiftPosition within RCC_CCIPRx.
maskMask for the RCC_CCIPRx field.
valClock value (0, 1, ... 7).

◆ STM32_CLOCK_BUS_AHB1

#define STM32_CLOCK_BUS_AHB1   0x048

Bus clocks.

◆ STM32_CLOCK_BUS_AHB2

#define STM32_CLOCK_BUS_AHB2   0x04c

◆ STM32_CLOCK_BUS_AHB3

#define STM32_CLOCK_BUS_AHB3   0x050

◆ STM32_CLOCK_BUS_APB1

#define STM32_CLOCK_BUS_APB1   0x058

◆ STM32_CLOCK_BUS_APB1_2

#define STM32_CLOCK_BUS_APB1_2   0x05c

◆ STM32_CLOCK_BUS_APB2

#define STM32_CLOCK_BUS_APB2   0x060

◆ STM32_CLOCK_MASK_MASK

#define STM32_CLOCK_MASK_MASK   0x7U

◆ STM32_CLOCK_MASK_SHIFT

#define STM32_CLOCK_MASK_SHIFT   13U

◆ STM32_CLOCK_REG_MASK

#define STM32_CLOCK_REG_MASK   0xFFU

◆ STM32_CLOCK_REG_SHIFT

#define STM32_CLOCK_REG_SHIFT   0U

◆ STM32_CLOCK_SHIFT_MASK

#define STM32_CLOCK_SHIFT_MASK   0x1FU

◆ STM32_CLOCK_SHIFT_SHIFT

#define STM32_CLOCK_SHIFT_SHIFT   8U

◆ STM32_CLOCK_VAL_MASK

#define STM32_CLOCK_VAL_MASK   0x7U

◆ STM32_CLOCK_VAL_SHIFT

#define STM32_CLOCK_VAL_SHIFT   16U

◆ STM32_PERIPH_BUS_MAX

#define STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB2

◆ STM32_PERIPH_BUS_MIN

#define STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1

◆ STM32_SRC_HSI

#define STM32_SRC_HSI   (STM32_SRC_LSI + 1)

Domain clocks.

System clock Fixed clocks

◆ STM32_SRC_HSI48

#define STM32_SRC_HSI48   (STM32_SRC_HSI + 1)

◆ STM32_SRC_MSI

#define STM32_SRC_MSI   (STM32_SRC_HSI48 + 1)

◆ STM32_SRC_PCLK

#define STM32_SRC_PCLK   (STM32_SRC_MSI + 1)

Bus clock.

◆ STM32_SRC_PLL_P

#define STM32_SRC_PLL_P   (STM32_SRC_PCLK + 1)

PLL clock outputs.

◆ STM32_SRC_PLL_Q

#define STM32_SRC_PLL_Q   (STM32_SRC_PLL_P + 1)

◆ STM32_SRC_PLL_R

#define STM32_SRC_PLL_R   (STM32_SRC_PLL_Q + 1)

◆ SWPMI1_SEL

#define SWPMI1_SEL (   val)    STM32_CLOCK(val, 1, 30, CCIPR_REG)

◆ UART4_SEL

#define UART4_SEL (   val)    STM32_CLOCK(val, 3, 6, CCIPR_REG)

◆ UART5_SEL

#define UART5_SEL (   val)    STM32_CLOCK(val, 3, 8, CCIPR_REG)

◆ USART1_SEL

#define USART1_SEL (   val)    STM32_CLOCK(val, 3, 0, CCIPR_REG)

Device domain clocks selection helpers.

CCIPR devices

◆ USART2_SEL

#define USART2_SEL (   val)    STM32_CLOCK(val, 3, 2, CCIPR_REG)

◆ USART3_SEL

#define USART3_SEL (   val)    STM32_CLOCK(val, 3, 4, CCIPR_REG)