stm32_adc.h File Reference

#include <zephyr/dt-bindings/adc/adc.h>

Go to the source code of this file.

Macros
#define	STM32_ADC_REG_MASK   BIT_MASK(8)
#define	STM32_ADC_REG_SHIFT   0U
#define	STM32_ADC_SHIFT_MASK   BIT_MASK(5)
#define	STM32_ADC_SHIFT_SHIFT   8U
#define	STM32_ADC_MASK_MASK   BIT_MASK(3)
#define	STM32_ADC_MASK_SHIFT   13U
#define	STM32_ADC_REG_VAL_MASK   BIT_MASK(3)
#define	STM32_ADC_REG_VAL_SHIFT   16U
#define	STM32_ADC_REAL_VAL_MASK   BIT_MASK(13)
#define	STM32_ADC_REAL_VAL_SHIFT   19U
#define	STM32_ADC(real_val, reg_val, mask, shift, reg)
	STM32 ADC configuration bit field.
#define	STM32_ADC_GET_REAL_VAL(val)    (((val) >> STM32_ADC_REAL_VAL_SHIFT) & STM32_ADC_REAL_VAL_MASK)
#define	STM32_ADC_GET_REG_VAL(val)    (((val) >> STM32_ADC_REG_VAL_SHIFT) & STM32_ADC_REG_VAL_MASK)
#define	STM32_ADC_GET_MASK(val)    (((val) >> STM32_ADC_MASK_SHIFT) & STM32_ADC_MASK_MASK)
#define	STM32_ADC_GET_SHIFT(val)    (((val) >> STM32_ADC_SHIFT_SHIFT) & STM32_ADC_SHIFT_MASK)
#define	STM32_ADC_GET_REG(val)    (((val) >> STM32_ADC_REG_SHIFT) & STM32_ADC_REG_MASK)
#define	STM32_ADC_RES(resolution, reg_val)
STM32 ADC clock source
This value is to set <st,adc-clock-source> One or both values may not apply to all series. Refer to the RefMan
#define	SYNC   1
#define	ASYNC   2
STM32 ADC sequencer type
This value is to set <st,adc-sequencer> One or both values may not apply to all series. Refer to the RefMan
#define	NOT_FULLY_CONFIGURABLE   0
#define	FULLY_CONFIGURABLE   1

Macro Definition Documentation

ASYNC

#define ASYNC   2

FULLY_CONFIGURABLE

#define FULLY_CONFIGURABLE   1

NOT_FULLY_CONFIGURABLE

#define NOT_FULLY_CONFIGURABLE   0

STM32_ADC

#define STM32_ADC	(		real_val,
			reg_val,
			mask,
			shift,
			reg
	)

Value:

 ((((reg) & STM32_ADC_REG_MASK) << STM32_ADC_REG_SHIFT) | \
 (((shift) & STM32_ADC_SHIFT_MASK) << STM32_ADC_SHIFT_SHIFT) | \
 (((mask) & STM32_ADC_MASK_MASK) << STM32_ADC_MASK_SHIFT) | \
 (((reg_val) & STM32_ADC_REG_VAL_MASK) << STM32_ADC_REG_VAL_SHIFT) | \
 (((real_val) & STM32_ADC_REAL_VAL_MASK) << STM32_ADC_REAL_VAL_SHIFT))

STM32 ADC configuration bit field.

• reg (0..0xFF) [ 0 : 7 ]
• shift (0..31) [ 8 : 12 ]
• mask (0x1, 0x3, 0x7) [ 13 : 15 ]
• reg_val (0..7) [ 16 : 18 ]
• real_val (0..8191) [ 19 : 31 ]

Parameters

reg	ADC_x register offset
shift	Position within ADC_x.
mask	Mask for the ADC_x field.
reg_val	Register value (0, 1, ... 7).
real_val	Real corresponding value (0, 1, ... 8191).

STM32_ADC_GET_MASK

#define STM32_ADC_GET_MASK

(

val

)

(((val) >> STM32_ADC_MASK_SHIFT) & STM32_ADC_MASK_MASK)

STM32_ADC_GET_REAL_VAL

#define STM32_ADC_GET_REAL_VAL

(

val

)

(((val) >> STM32_ADC_REAL_VAL_SHIFT) & STM32_ADC_REAL_VAL_MASK)

STM32_ADC_GET_REG

#define STM32_ADC_GET_REG

(

val

)

(((val) >> STM32_ADC_REG_SHIFT) & STM32_ADC_REG_MASK)

STM32_ADC_GET_REG_VAL

#define STM32_ADC_GET_REG_VAL

(

val

)

(((val) >> STM32_ADC_REG_VAL_SHIFT) & STM32_ADC_REG_VAL_MASK)

STM32_ADC_GET_SHIFT

#define STM32_ADC_GET_SHIFT

(

val

)

(((val) >> STM32_ADC_SHIFT_SHIFT) & STM32_ADC_SHIFT_MASK)

STM32_ADC_MASK_MASK

#define STM32_ADC_MASK_MASK   BIT_MASK(3)

STM32_ADC_MASK_SHIFT

#define STM32_ADC_MASK_SHIFT   13U

STM32_ADC_REAL_VAL_MASK

#define STM32_ADC_REAL_VAL_MASK   BIT_MASK(13)

STM32_ADC_REAL_VAL_SHIFT

#define STM32_ADC_REAL_VAL_SHIFT   19U

STM32_ADC_REG_MASK

#define STM32_ADC_REG_MASK   BIT_MASK(8)

STM32_ADC_REG_SHIFT

#define STM32_ADC_REG_SHIFT   0U

STM32_ADC_REG_VAL_MASK

#define STM32_ADC_REG_VAL_MASK   BIT_MASK(3)

STM32_ADC_REG_VAL_SHIFT

#define STM32_ADC_REG_VAL_SHIFT   16U

STM32_ADC_RES

#define STM32_ADC_RES	(		resolution,
			reg_val
	)

Value:

 STM32_ADC(resolution, reg_val, STM32_ADC_RES_MASK, STM32_ADC_RES_SHIFT, \
 STM32_ADC_RES_REG)

STM32_ADC_SHIFT_MASK

#define STM32_ADC_SHIFT_MASK   BIT_MASK(5)

STM32_ADC_SHIFT_SHIFT

#define STM32_ADC_SHIFT_SHIFT   8U

SYNC

#define SYNC   1