Zephyr API Documentation  3.6.99
A Scalable Open Source RTOS
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pinctrl-rcar-common.h File Reference

Go to the source code of this file.

Macros

#define IPSR(bank, shift, func)   (((bank) << 10U) | ((shift) << 4U) | (func))
 Utility macro to build IPSR property entry.
 
#define PIN_NOGPSR_START   1024U
 
#define RCAR_GP_PIN(bank, pin)   (((bank) * 32U) + (pin))
 Utility macro to encode a GPIO capable pin.
 
#define RCAR_NOGP_PIN(pin)   (PIN_NOGPSR_START + pin)
 Utility macro to encode a non capable GPIO pin.
 
#define IPnSR(bank, reg, shift, func)    IPSR(((reg) << 5U) | (bank), shift, func)
 
#define IP0SR0(shift, func)   IPnSR(0, 0, shift, func)
 
#define IP1SR0(shift, func)   IPnSR(1, 0, shift, func)
 
#define IP2SR0(shift, func)   IPnSR(2, 0, shift, func)
 
#define IP3SR0(shift, func)   IPnSR(3, 0, shift, func)
 
#define IP0SR1(shift, func)   IPnSR(0, 1, shift, func)
 
#define IP1SR1(shift, func)   IPnSR(1, 1, shift, func)
 
#define IP2SR1(shift, func)   IPnSR(2, 1, shift, func)
 
#define IP3SR1(shift, func)   IPnSR(3, 1, shift, func)
 
#define IP0SR2(shift, func)   IPnSR(0, 2, shift, func)
 
#define IP1SR2(shift, func)   IPnSR(1, 2, shift, func)
 
#define IP2SR2(shift, func)   IPnSR(2, 2, shift, func)
 
#define IP3SR2(shift, func)   IPnSR(3, 2, shift, func)
 
#define IP0SR3(shift, func)   IPnSR(0, 3, shift, func)
 
#define IP1SR3(shift, func)   IPnSR(1, 3, shift, func)
 
#define IP2SR3(shift, func)   IPnSR(2, 3, shift, func)
 
#define IP3SR3(shift, func)   IPnSR(3, 3, shift, func)
 
#define IP0SR4(shift, func)   IPnSR(0, 4, shift, func)
 
#define IP1SR4(shift, func)   IPnSR(1, 4, shift, func)
 
#define IP2SR4(shift, func)   IPnSR(2, 4, shift, func)
 
#define IP3SR4(shift, func)   IPnSR(3, 4, shift, func)
 
#define IP0SR5(shift, func)   IPnSR(0, 5, shift, func)
 
#define IP1SR5(shift, func)   IPnSR(1, 5, shift, func)
 
#define IP2SR5(shift, func)   IPnSR(2, 5, shift, func)
 
#define IP3SR5(shift, func)   IPnSR(3, 5, shift, func)
 
#define IP0SR6(shift, func)   IPnSR(0, 6, shift, func)
 
#define IP1SR6(shift, func)   IPnSR(1, 6, shift, func)
 
#define IP2SR6(shift, func)   IPnSR(2, 6, shift, func)
 
#define IP3SR6(shift, func)   IPnSR(3, 6, shift, func)
 
#define IP0SR7(shift, func)   IPnSR(0, 7, shift, func)
 
#define IP1SR7(shift, func)   IPnSR(1, 7, shift, func)
 
#define IP2SR7(shift, func)   IPnSR(2, 7, shift, func)
 
#define IP3SR7(shift, func)   IPnSR(3, 7, shift, func)
 
#define IPSR_DUMMY   IPnSR(0x1f, 7, 0x1f, 0xf)
 Macro to define a dummy IPSR flag for a pin.
 
#define PIN_VOLTAGE_NONE   0
 
#define PIN_VOLTAGE_1P8V   1
 
#define PIN_VOLTAGE_3P3V   2
 

Macro Definition Documentation

◆ IP0SR0

#define IP0SR0 (   shift,
  func 
)    IPnSR(0, 0, shift, func)

◆ IP0SR1

#define IP0SR1 (   shift,
  func 
)    IPnSR(0, 1, shift, func)

◆ IP0SR2

#define IP0SR2 (   shift,
  func 
)    IPnSR(0, 2, shift, func)

◆ IP0SR3

#define IP0SR3 (   shift,
  func 
)    IPnSR(0, 3, shift, func)

◆ IP0SR4

#define IP0SR4 (   shift,
  func 
)    IPnSR(0, 4, shift, func)

◆ IP0SR5

#define IP0SR5 (   shift,
  func 
)    IPnSR(0, 5, shift, func)

◆ IP0SR6

#define IP0SR6 (   shift,
  func 
)    IPnSR(0, 6, shift, func)

◆ IP0SR7

#define IP0SR7 (   shift,
  func 
)    IPnSR(0, 7, shift, func)

◆ IP1SR0

#define IP1SR0 (   shift,
  func 
)    IPnSR(1, 0, shift, func)

◆ IP1SR1

#define IP1SR1 (   shift,
  func 
)    IPnSR(1, 1, shift, func)

◆ IP1SR2

#define IP1SR2 (   shift,
  func 
)    IPnSR(1, 2, shift, func)

◆ IP1SR3

#define IP1SR3 (   shift,
  func 
)    IPnSR(1, 3, shift, func)

◆ IP1SR4

#define IP1SR4 (   shift,
  func 
)    IPnSR(1, 4, shift, func)

◆ IP1SR5

#define IP1SR5 (   shift,
  func 
)    IPnSR(1, 5, shift, func)

◆ IP1SR6

#define IP1SR6 (   shift,
  func 
)    IPnSR(1, 6, shift, func)

◆ IP1SR7

#define IP1SR7 (   shift,
  func 
)    IPnSR(1, 7, shift, func)

◆ IP2SR0

#define IP2SR0 (   shift,
  func 
)    IPnSR(2, 0, shift, func)

◆ IP2SR1

#define IP2SR1 (   shift,
  func 
)    IPnSR(2, 1, shift, func)

◆ IP2SR2

#define IP2SR2 (   shift,
  func 
)    IPnSR(2, 2, shift, func)

◆ IP2SR3

#define IP2SR3 (   shift,
  func 
)    IPnSR(2, 3, shift, func)

◆ IP2SR4

#define IP2SR4 (   shift,
  func 
)    IPnSR(2, 4, shift, func)

◆ IP2SR5

#define IP2SR5 (   shift,
  func 
)    IPnSR(2, 5, shift, func)

◆ IP2SR6

#define IP2SR6 (   shift,
  func 
)    IPnSR(2, 6, shift, func)

◆ IP2SR7

#define IP2SR7 (   shift,
  func 
)    IPnSR(2, 7, shift, func)

◆ IP3SR0

#define IP3SR0 (   shift,
  func 
)    IPnSR(3, 0, shift, func)

◆ IP3SR1

#define IP3SR1 (   shift,
  func 
)    IPnSR(3, 1, shift, func)

◆ IP3SR2

#define IP3SR2 (   shift,
  func 
)    IPnSR(3, 2, shift, func)

◆ IP3SR3

#define IP3SR3 (   shift,
  func 
)    IPnSR(3, 3, shift, func)

◆ IP3SR4

#define IP3SR4 (   shift,
  func 
)    IPnSR(3, 4, shift, func)

◆ IP3SR5

#define IP3SR5 (   shift,
  func 
)    IPnSR(3, 5, shift, func)

◆ IP3SR6

#define IP3SR6 (   shift,
  func 
)    IPnSR(3, 6, shift, func)

◆ IP3SR7

#define IP3SR7 (   shift,
  func 
)    IPnSR(3, 7, shift, func)

◆ IPnSR

#define IPnSR (   bank,
  reg,
  shift,
  func 
)     IPSR(((reg) << 5U) | (bank), shift, func)

◆ IPSR

#define IPSR (   bank,
  shift,
  func 
)    (((bank) << 10U) | ((shift) << 4U) | (func))

Utility macro to build IPSR property entry.

IPSR: Peripheral Function Select Register Each IPSR bank can hold 8 cellules of 4 bits coded function.

Parameters
bankthe IPSR register bank.
shiftthe bit shift for this alternate function.
functhe 4 bits encoded alternate function.

Function code [ 0 : 3 ] Function shift [ 4 : 8 ] Empty [ 9 ] IPSR bank [ 10 : 14 ] Register index [ 15 : 17 ] (S4 only)

◆ IPSR_DUMMY

#define IPSR_DUMMY   IPnSR(0x1f, 7, 0x1f, 0xf)

Macro to define a dummy IPSR flag for a pin.

This macro is used to define a dummy IPSR flag for a pin in the R-Car PFC driver. It is intended for pins that do not have a specific function defined in IPSR but always act as a peripheral. The dummy IPSR flag ensures that the driver sets the 'peripheral' bit for such pins.

See also
RCAR_PIN_FLAGS_FUNC_DUMMY

◆ PIN_NOGPSR_START

#define PIN_NOGPSR_START   1024U

◆ PIN_VOLTAGE_1P8V

#define PIN_VOLTAGE_1P8V   1

◆ PIN_VOLTAGE_3P3V

#define PIN_VOLTAGE_3P3V   2

◆ PIN_VOLTAGE_NONE

#define PIN_VOLTAGE_NONE   0

◆ RCAR_GP_PIN

#define RCAR_GP_PIN (   bank,
  pin 
)    (((bank) * 32U) + (pin))

Utility macro to encode a GPIO capable pin.

Parameters
bankthe GPIO bank
pinthe pin within the GPIO bank (0..31)

◆ RCAR_NOGP_PIN

#define RCAR_NOGP_PIN (   pin)    (PIN_NOGPSR_START + pin)

Utility macro to encode a non capable GPIO pin.

Parameters
pinthe encoded pin number