Zephyr API Documentation  3.6.99
A Scalable Open Source RTOS
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loapic.h
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1/* loapic.h - public LOAPIC APIs */
2
3/*
4 * Copyright (c) 2015 Wind River Systems, Inc.
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9#ifndef ZEPHYR_INCLUDE_DRIVERS_LOAPIC_H_
10#define ZEPHYR_INCLUDE_DRIVERS_LOAPIC_H_
11
12#include <zephyr/arch/cpu.h>
13#include <zephyr/arch/x86/msr.h>
15
16/* Local APIC Register Offset */
17
18#define LOAPIC_ID 0x020 /* Local APIC ID Reg */
19#define LOAPIC_VER 0x030 /* Local APIC Version Reg */
20#define LOAPIC_TPR 0x080 /* Task Priority Reg */
21#define LOAPIC_APR 0x090 /* Arbitration Priority Reg */
22#define LOAPIC_PPR 0x0a0 /* Processor Priority Reg */
23#define LOAPIC_EOI 0x0b0 /* EOI Reg */
24#define LOAPIC_LDR 0x0d0 /* Logical Destination Reg */
25#define LOAPIC_DFR 0x0e0 /* Destination Format Reg */
26#define LOAPIC_SVR 0x0f0 /* Spurious Interrupt Reg */
27#define LOAPIC_ISR 0x100 /* In-service Reg */
28#define LOAPIC_TMR 0x180 /* Trigger Mode Reg */
29#define LOAPIC_IRR 0x200 /* Interrupt Request Reg */
30#define LOAPIC_ESR 0x280 /* Error Status Reg */
31#define LOAPIC_ICRLO 0x300 /* Interrupt Command Reg */
32#define LOAPIC_ICRHI 0x310 /* Interrupt Command Reg */
33#define LOAPIC_TIMER 0x320 /* LVT (Timer) */
34#define LOAPIC_THERMAL 0x330 /* LVT (Thermal) */
35#define LOAPIC_PMC 0x340 /* LVT (PMC) */
36#define LOAPIC_LINT0 0x350 /* LVT (LINT0) */
37#define LOAPIC_LINT1 0x360 /* LVT (LINT1) */
38#define LOAPIC_ERROR 0x370 /* LVT (ERROR) */
39#define LOAPIC_TIMER_ICR 0x380 /* Timer Initial Count Reg */
40#define LOAPIC_TIMER_CCR 0x390 /* Timer Current Count Reg */
41#define LOAPIC_TIMER_CONFIG 0x3e0 /* Timer Divide Config Reg */
42#define LOAPIC_SELF_IPI 0x3f0 /* Self IPI Reg, only support in X2APIC mode */
43
44#define LOAPIC_ICR_BUSY 0x00001000 /* delivery status: 1 = busy */
45
46#define LOAPIC_ICR_IPI_OTHERS 0x000C4000U /* normal IPI to other CPUs */
47#define LOAPIC_ICR_IPI_INIT 0x00004500U
48#define LOAPIC_ICR_IPI_STARTUP 0x00004600U
49
50#define LOAPIC_LVT_MASKED 0x00010000 /* mask */
51
52/* Defined in intc_loapic.c */
53#define LOAPIC_REGS_STR loapic_regs /* mmio device name */
54
55#ifndef _ASMLANGUAGE
56
57#ifdef __cplusplus
58extern "C" {
59#endif
60
62
63uint32_t z_loapic_irq_base(void);
64void z_loapic_enable(unsigned char cpu_number);
65void z_loapic_int_vec_set(unsigned int irq, unsigned int vector);
66void z_loapic_irq_enable(unsigned int irq);
67void z_loapic_irq_disable(unsigned int irq);
68
74static inline uint64_t x86_read_x2apic(unsigned int reg)
75{
76 reg >>= 4;
77 return z_x86_msr_read(X86_X2APIC_BASE_MSR + reg);
78}
79
85static inline uint32_t x86_read_xapic(unsigned int reg)
86{
87 mm_reg_t base;
89 return sys_read32(base + reg);
90}
91
102static inline uint32_t x86_read_loapic(unsigned int reg)
103{
104#ifdef CONFIG_X2APIC
105 return x86_read_x2apic(reg);
106#else
107 return x86_read_xapic(reg);
108#endif
109}
110
117static inline void x86_write_x2apic(unsigned int reg, uint64_t val)
118{
119 reg >>= 4;
120 z_x86_msr_write(X86_X2APIC_BASE_MSR + reg, val);
121}
122
129static inline void x86_write_xapic(unsigned int reg, uint32_t val)
130{
131 mm_reg_t base;
133 sys_write32(val, base + reg);
134}
135
147static inline void x86_write_loapic(unsigned int reg, uint32_t val)
148{
149#ifdef CONFIG_X2APIC
150 x86_write_x2apic(reg, val);
151#else
152 x86_write_xapic(reg, val);
153#endif
154}
155
163static inline void z_loapic_ipi(uint8_t apic_id, uint32_t ipi, uint8_t vector)
164{
165 ipi |= vector;
166
167#ifndef CONFIG_X2APIC
168 /*
169 * Legacy xAPIC mode: first wait for any previous IPI to be delivered.
170 */
171
173 }
174
175 x86_write_xapic(LOAPIC_ICRHI, apic_id << 24);
177#else
178 /*
179 * x2APIC mode is greatly simplified: one write, no delivery status.
180 */
181
182 x86_write_x2apic(LOAPIC_ICRLO, (((uint64_t) apic_id) << 32) | ipi);
183#endif
184}
185
186#ifdef __cplusplus
187}
188#endif
189
190#endif /* _ASMLANGUAGE */
191
192#endif /* ZEPHYR_INCLUDE_DRIVERS_LOAPIC_H_ */
#define DEVICE_MMIO_TOPLEVEL_DECLARE(name)
Provide an extern reference to a top-level MMIO region.
Definition: device_mmio.h:638
#define DEVICE_MMIO_TOPLEVEL_GET(name)
Obtain the MMIO address for a device declared top-level.
Definition: device_mmio.h:734
static void x86_write_x2apic(unsigned int reg, uint64_t val)
Write 64-bit value to the local APIC in x2APIC mode.
Definition: loapic.h:117
#define LOAPIC_ICRLO
Definition: loapic.h:31
static uint32_t x86_read_xapic(unsigned int reg)
Read 32-bit value from the local APIC in xAPIC (MMIO) mode.
Definition: loapic.h:85
#define LOAPIC_ICRHI
Definition: loapic.h:32
static uint32_t x86_read_loapic(unsigned int reg)
Read value from the local APIC using the default mode.
Definition: loapic.h:102
static uint64_t x86_read_x2apic(unsigned int reg)
Read 64-bit value from the local APIC in x2APIC mode.
Definition: loapic.h:74
#define LOAPIC_ICR_BUSY
Definition: loapic.h:44
#define LOAPIC_REGS_STR
Definition: loapic.h:53
static void x86_write_loapic(unsigned int reg, uint32_t val)
Write 32-bit value to the local APIC using the default mode.
Definition: loapic.h:147
static void x86_write_xapic(unsigned int reg, uint32_t val)
Write 32-bit value to the local APIC in xAPIC (MMIO) mode.
Definition: loapic.h:129
#define X86_X2APIC_BASE_MSR
Definition: msr.h:25
__UINT32_TYPE__ uint32_t
Definition: stdint.h:90
__UINT64_TYPE__ uint64_t
Definition: stdint.h:91
__UINT8_TYPE__ uint8_t
Definition: stdint.h:88
static ALWAYS_INLINE void sys_write32(uint32_t data, mem_addr_t addr)
Definition: sys-io-common.h:70
static ALWAYS_INLINE uint32_t sys_read32(mem_addr_t addr)
Definition: sys-io-common.h:59
uintptr_t mm_reg_t
Definition: sys_io.h:20