Zephyr API Documentation  3.6.99
A Scalable Open Source RTOS
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pcie.h
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1/*
2 * Copyright (c) 2019 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#ifndef ZEPHYR_INCLUDE_DRIVERS_PCIE_PCIE_H_
8#define ZEPHYR_INCLUDE_DRIVERS_PCIE_PCIE_H_
9
17#include <stddef.h>
18#include <zephyr/devicetree.h>
20#include <zephyr/types.h>
21#include <zephyr/kernel.h>
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
38
48
49/* Helper macro to exclude invalid PCIe identifiers. We should really only
50 * need to look for PCIE_ID_NONE, but because of some broken PCI host controllers
51 * we have try cases where both VID & DID are zero or just one of them is
52 * zero (0x0000) and the other is all ones (0xFFFF).
53 */
54#define PCIE_ID_IS_VALID(id) ((id != PCIE_ID_NONE) && \
55 (id != PCIE_ID(0x0000, 0x0000)) && \
56 (id != PCIE_ID(0xFFFF, 0x0000)) && \
57 (id != PCIE_ID(0x0000, 0xFFFF)))
58
59struct pcie_dev {
64};
65
66#define Z_DEVICE_PCIE_NAME(node_id) _CONCAT(pcie_dev_, DT_DEP_ORD(node_id))
67
74#define PCIE_DT_ID(node_id) PCIE_ID(DT_PROP_OR(node_id, vendor_id, 0xffff), \
75 DT_PROP_OR(node_id, device_id, 0xffff))
76
86#define PCIE_DT_INST_ID(inst) PCIE_DT_ID(DT_DRV_INST(inst))
87
96#define DEVICE_PCIE_DECLARE(node_id) \
97 STRUCT_SECTION_ITERABLE(pcie_dev, Z_DEVICE_PCIE_NAME(node_id)) = { \
98 .bdf = PCIE_BDF_NONE, \
99 .id = PCIE_DT_ID(node_id), \
100 .class_rev = DT_PROP_OR(node_id, class_rev, 0), \
101 .class_rev_mask = DT_PROP_OR(node_id, class_rev_mask, 0), \
102 }
103
112#define DEVICE_PCIE_INST_DECLARE(inst) DEVICE_PCIE_DECLARE(DT_DRV_INST(inst))
113
138#define DEVICE_PCIE_INIT(node_id, name) .name = &Z_DEVICE_PCIE_NAME(node_id)
139
149#define DEVICE_PCIE_INST_INIT(inst, name) \
150 DEVICE_PCIE_INIT(DT_DRV_INST(inst), name)
151
152struct pcie_bar {
154 size_t size;
155};
156
157/*
158 * These functions are arch-, board-, or SoC-specific.
159 */
160
170extern uint32_t pcie_conf_read(pcie_bdf_t bdf, unsigned int reg);
171
181extern void pcie_conf_write(pcie_bdf_t bdf, unsigned int reg, uint32_t data);
182
191typedef bool (*pcie_scan_cb_t)(pcie_bdf_t bdf, pcie_id_t id, void *cb_data);
192
193enum {
198};
199
204
207
209 void *cb_data;
210
213};
214
222int pcie_scan(const struct pcie_scan_opt *opt);
223
231extern bool pcie_get_mbar(pcie_bdf_t bdf,
232 unsigned int bar_index,
233 struct pcie_bar *mbar);
234
249 unsigned int index,
250 struct pcie_bar *mbar);
251
260 unsigned int bar_index,
261 struct pcie_bar *iobar);
262
277 unsigned int index,
278 struct pcie_bar *iobar);
279
287extern void pcie_set_cmd(pcie_bdf_t bdf, uint32_t bits, bool on);
288
289#ifndef CONFIG_PCIE_CONTROLLER
303extern unsigned int pcie_alloc_irq(pcie_bdf_t bdf);
304#endif /* CONFIG_PCIE_CONTROLLER */
305
312extern unsigned int pcie_get_irq(pcie_bdf_t bdf);
313
326extern void pcie_irq_enable(pcie_bdf_t bdf, unsigned int irq);
327
336
345
358 unsigned int irq,
359 unsigned int priority,
360 void (*routine)(const void *parameter),
361 const void *parameter,
363
374#define PCIE_HOST_CONTROLLER(n) PCIE_BDF(0, 0, n)
375
376/*
377 * Configuration word 13 contains the head of the capabilities list.
378 */
379
380#define PCIE_CONF_CAPPTR 13U /* capabilities pointer */
381#define PCIE_CONF_CAPPTR_FIRST(w) (((w) >> 2) & 0x3FU)
382
383/*
384 * The first word of every capability contains a capability identifier,
385 * and a link to the next capability (or 0) in configuration space.
386 */
387
388#define PCIE_CONF_CAP_ID(w) ((w) & 0xFFU)
389#define PCIE_CONF_CAP_NEXT(w) (((w) >> 10) & 0x3FU)
390
391/*
392 * The extended PCI Express capabilities lie at the end of the PCI configuration space
393 */
394
395#define PCIE_CONF_EXT_CAPPTR 64U
396
397/*
398 * The first word of every capability contains an extended capability identifier,
399 * and a link to the next capability (or 0) in the extended configuration space.
400 */
401
402#define PCIE_CONF_EXT_CAP_ID(w) ((w) & 0xFFFFU)
403#define PCIE_CONF_EXT_CAP_VER(w) (((w) >> 16) & 0xFU)
404#define PCIE_CONF_EXT_CAP_NEXT(w) (((w) >> 20) & 0xFFFU)
405
406/*
407 * Configuration word 0 aligns directly with pcie_id_t.
408 */
409
410#define PCIE_CONF_ID 0U
411
412/*
413 * Configuration word 1 contains command and status bits.
414 */
415
416#define PCIE_CONF_CMDSTAT 1U /* command/status register */
417
418#define PCIE_CONF_CMDSTAT_IO 0x00000001U /* I/O access enable */
419#define PCIE_CONF_CMDSTAT_MEM 0x00000002U /* mem access enable */
420#define PCIE_CONF_CMDSTAT_MASTER 0x00000004U /* bus master enable */
421#define PCIE_CONF_CMDSTAT_INTERRUPT 0x00080000U /* interrupt status */
422#define PCIE_CONF_CMDSTAT_CAPS 0x00100000U /* capabilities list */
423
424/*
425 * Configuration word 2 has additional function identification that
426 * we only care about for debug output (PCIe shell commands).
427 */
428
429#define PCIE_CONF_CLASSREV 2U /* class/revision register */
430
431#define PCIE_CONF_CLASSREV_CLASS(w) (((w) >> 24) & 0xFFU)
432#define PCIE_CONF_CLASSREV_SUBCLASS(w) (((w) >> 16) & 0xFFU)
433#define PCIE_CONF_CLASSREV_PROGIF(w) (((w) >> 8) & 0xFFU)
434#define PCIE_CONF_CLASSREV_REV(w) ((w) & 0xFFU)
435
436/*
437 * The only part of configuration word 3 that is of interest to us is
438 * the header type, as we use it to distinguish functional endpoints
439 * from bridges (which are, for our purposes, transparent).
440 */
441
442#define PCIE_CONF_TYPE 3U
443
444#define PCIE_CONF_MULTIFUNCTION(w) (((w) & 0x00800000U) != 0U)
445#define PCIE_CONF_TYPE_BRIDGE(w) (((w) & 0x007F0000U) != 0U)
446#define PCIE_CONF_TYPE_GET(w) (((w) >> 16) & 0x7F)
447
448#define PCIE_CONF_TYPE_STANDARD 0x0U
449#define PCIE_CONF_TYPE_PCI_BRIDGE 0x1U
450#define PCIE_CONF_TYPE_CARDBUS_BRIDGE 0x2U
451
452/*
453 * Words 4-9 are BARs are I/O or memory decoders. Memory decoders may
454 * be 64-bit decoders, in which case the next configuration word holds
455 * the high-order bits (and is, thus, not a BAR itself).
456 */
457
458#define PCIE_CONF_BAR0 4U
459#define PCIE_CONF_BAR1 5U
460#define PCIE_CONF_BAR2 6U
461#define PCIE_CONF_BAR3 7U
462#define PCIE_CONF_BAR4 8U
463#define PCIE_CONF_BAR5 9U
464
465#define PCIE_CONF_BAR_IO(w) (((w) & 0x00000001U) == 0x00000001U)
466#define PCIE_CONF_BAR_MEM(w) (((w) & 0x00000001U) != 0x00000001U)
467#define PCIE_CONF_BAR_64(w) (((w) & 0x00000006U) == 0x00000004U)
468#define PCIE_CONF_BAR_ADDR(w) ((w) & ~0xfUL)
469#define PCIE_CONF_BAR_IO_ADDR(w) ((w) & ~0x3UL)
470#define PCIE_CONF_BAR_FLAGS(w) ((w) & 0xfUL)
471#define PCIE_CONF_BAR_NONE 0U
472
473#define PCIE_CONF_BAR_INVAL 0xFFFFFFF0U
474#define PCIE_CONF_BAR_INVAL64 0xFFFFFFFFFFFFFFF0UL
475
476#define PCIE_CONF_BAR_INVAL_FLAGS(w) \
477 ((((w) & 0x00000006U) == 0x00000006U) || \
478 (((w) & 0x00000006U) == 0x00000002U))
479
480/*
481 * Type 1 Header has files related to bus management
482 */
483#define PCIE_BUS_NUMBER 6U
484
485#define PCIE_BUS_PRIMARY_NUMBER(w) ((w) & 0xffUL)
486#define PCIE_BUS_SECONDARY_NUMBER(w) (((w) >> 8) & 0xffUL)
487#define PCIE_BUS_SUBORDINATE_NUMBER(w) (((w) >> 16) & 0xffUL)
488#define PCIE_SECONDARY_LATENCY_TIMER(w) (((w) >> 24) & 0xffUL)
489
490#define PCIE_BUS_NUMBER_VAL(prim, sec, sub, lat) \
491 (((prim) & 0xffUL) | \
492 (((sec) & 0xffUL) << 8) | \
493 (((sub) & 0xffUL) << 16) | \
494 (((lat) & 0xffUL) << 24))
495
496/*
497 * Type 1 words 7 to 12 setups Bridge Memory base and limits
498 */
499#define PCIE_IO_SEC_STATUS 7U
500
501#define PCIE_IO_BASE(w) ((w) & 0xffUL)
502#define PCIE_IO_LIMIT(w) (((w) >> 8) & 0xffUL)
503#define PCIE_SEC_STATUS(w) (((w) >> 16) & 0xffffUL)
504
505#define PCIE_IO_SEC_STATUS_VAL(iob, iol, sec_status) \
506 (((iob) & 0xffUL) | \
507 (((iol) & 0xffUL) << 8) | \
508 (((sec_status) & 0xffffUL) << 16))
509
510#define PCIE_MEM_BASE_LIMIT 8U
511
512#define PCIE_MEM_BASE(w) ((w) & 0xffffUL)
513#define PCIE_MEM_LIMIT(w) (((w) >> 16) & 0xffffUL)
514
515#define PCIE_MEM_BASE_LIMIT_VAL(memb, meml) \
516 (((memb) & 0xffffUL) | \
517 (((meml) & 0xffffUL) << 16))
518
519#define PCIE_PREFETCH_BASE_LIMIT 9U
520
521#define PCIE_PREFETCH_BASE(w) ((w) & 0xffffUL)
522#define PCIE_PREFETCH_LIMIT(w) (((w) >> 16) & 0xffffUL)
523
524#define PCIE_PREFETCH_BASE_LIMIT_VAL(pmemb, pmeml) \
525 (((pmemb) & 0xffffUL) | \
526 (((pmeml) & 0xffffUL) << 16))
527
528#define PCIE_PREFETCH_BASE_UPPER 10U
529
530#define PCIE_PREFETCH_LIMIT_UPPER 11U
531
532#define PCIE_IO_BASE_LIMIT_UPPER 12U
533
534#define PCIE_IO_BASE_UPPER(w) ((w) & 0xffffUL)
535#define PCIE_IO_LIMIT_UPPER(w) (((w) >> 16) & 0xffffUL)
536
537#define PCIE_IO_BASE_LIMIT_UPPER_VAL(iobu, iolu) \
538 (((iobu) & 0xffffUL) | \
539 (((iolu) & 0xffffUL) << 16))
540
541/*
542 * Word 15 contains information related to interrupts.
543 *
544 * We're only interested in the low byte, which is [supposed to be] set by
545 * the firmware to indicate which wire IRQ the device interrupt is routed to.
546 */
547
548#define PCIE_CONF_INTR 15U
549
550#define PCIE_CONF_INTR_IRQ(w) ((w) & 0xFFU)
551#define PCIE_CONF_INTR_IRQ_NONE 0xFFU /* no interrupt routed */
552
553#define PCIE_MAX_BUS (0xFFFFFFFFU & PCIE_BDF_BUS_MASK)
554#define PCIE_MAX_DEV (0xFFFFFFFFU & PCIE_BDF_DEV_MASK)
555#define PCIE_MAX_FUNC (0xFFFFFFFFU & PCIE_BDF_FUNC_MASK)
556
571#define PCIE_IRQ_CONNECT(bdf_p, irq_p, priority_p, \
572 isr_p, isr_param_p, flags_p) \
573 ARCH_PCIE_IRQ_CONNECT(bdf_p, irq_p, priority_p, \
574 isr_p, isr_param_p, flags_p)
575
576#ifdef __cplusplus
577}
578#endif
579
584#endif /* ZEPHYR_INCLUDE_DRIVERS_PCIE_PCIE_H_ */
Devicetree main header.
uint32_t pcie_conf_read(pcie_bdf_t bdf, unsigned int reg)
Read a 32-bit word from an endpoint's configuration space.
bool pcie_connect_dynamic_irq(pcie_bdf_t bdf, unsigned int irq, unsigned int priority, void(*routine)(const void *parameter), const void *parameter, uint32_t flags)
Dynamically connect a PCIe endpoint IRQ to an ISR handler.
void pcie_set_cmd(pcie_bdf_t bdf, uint32_t bits, bool on)
Set or reset bits in the endpoint command/status register.
bool pcie_get_iobar(pcie_bdf_t bdf, unsigned int bar_index, struct pcie_bar *iobar)
Get the I/O BAR at a specific BAR index.
uint32_t pcie_id_t
A unique PCI(e) identifier (vendor ID, device ID).
Definition: pcie.h:47
void pcie_conf_write(pcie_bdf_t bdf, unsigned int reg, uint32_t data)
Write a 32-bit word to an endpoint's configuration space.
uint32_t pcie_get_cap(pcie_bdf_t bdf, uint32_t cap_id)
Find a PCI(e) capability in an endpoint's configuration space.
uint32_t pcie_get_ext_cap(pcie_bdf_t bdf, uint32_t cap_id)
Find an Extended PCI(e) capability in an endpoint's configuration space.
uint32_t pcie_bdf_t
A unique PCI(e) endpoint (bus, device, function).
Definition: pcie.h:37
bool(* pcie_scan_cb_t)(pcie_bdf_t bdf, pcie_id_t id, void *cb_data)
Callback type used for scanning for PCI endpoints.
Definition: pcie.h:191
int pcie_scan(const struct pcie_scan_opt *opt)
Scan for PCIe devices.
bool pcie_probe_iobar(pcie_bdf_t bdf, unsigned int index, struct pcie_bar *iobar)
Probe the nth I/O BAR address assigned to an endpoint.
unsigned int pcie_alloc_irq(pcie_bdf_t bdf)
Allocate an IRQ for an endpoint.
bool pcie_probe_mbar(pcie_bdf_t bdf, unsigned int index, struct pcie_bar *mbar)
Probe the nth MMIO address assigned to an endpoint.
bool pcie_get_mbar(pcie_bdf_t bdf, unsigned int bar_index, struct pcie_bar *mbar)
Get the MBAR at a specific BAR index.
unsigned int pcie_get_irq(pcie_bdf_t bdf)
Return the IRQ assigned by the firmware/board to an endpoint.
void pcie_irq_enable(pcie_bdf_t bdf, unsigned int irq)
Enable the PCI(e) endpoint to generate the specified IRQ.
@ PCIE_SCAN_RECURSIVE
Scan all available PCI host controllers and sub-busses.
Definition: pcie.h:195
@ PCIE_SCAN_CB_ALL
Do the callback for all endpoint types, including bridges.
Definition: pcie.h:197
#define BIT(n)
Unsigned integer with bit position n set (signed in assembly language).
Definition: util_macro.h:44
Public kernel APIs.
flags
Definition: parser.h:96
#define bool
Definition: stdbool.h:13
__UINT32_TYPE__ uint32_t
Definition: stdint.h:90
__UINT8_TYPE__ uint8_t
Definition: stdint.h:88
__UINTPTR_TYPE__ uintptr_t
Definition: stdint.h:105
Definition: pcie.h:152
uintptr_t phys_addr
Definition: pcie.h:153
size_t size
Definition: pcie.h:154
Definition: pcie.h:59
pcie_id_t id
Definition: pcie.h:61
uint32_t class_rev_mask
Definition: pcie.h:63
pcie_bdf_t bdf
Definition: pcie.h:60
uint32_t class_rev
Definition: pcie.h:62
Options for performing a scan for PCI devices.
Definition: pcie.h:201
uint8_t bus
Initial bus number to scan.
Definition: pcie.h:203
void * cb_data
Custom data to pass to the scan callback.
Definition: pcie.h:209
pcie_scan_cb_t cb
Function to call for each found endpoint.
Definition: pcie.h:206
uint32_t flags
Scan flags.
Definition: pcie.h:212