Go to the source code of this file.
◆ CLINT_BASE
#define CLINT_BASE 0x02000000 |
◆ CLINT_SIZE
#define CLINT_SIZE 0x000c0000 |
◆ csr_clear
#define csr_clear |
( |
| csr, |
|
|
| val ) |
Value:({ \
unsigned long __cv = (unsigned long)(val); \
__asm__
volatile (
"csrc " STRINGIFY(csr)
", %0" \
: : "rK" (__cv) \
: "memory"); \
})
#define STRINGIFY(s)
Definition common.h:134
◆ csr_read
Value:({ \
register unsigned long __rv; \
__asm__
volatile (
"csrr %0, " STRINGIFY(csr) \
: "=r" (__rv)); \
__rv; \
})
◆ csr_read_clear
#define csr_read_clear |
( |
| csr, |
|
|
| val ) |
Value:({ \
unsigned long __rcv = (unsigned long)(val); \
__asm__
volatile (
"csrrc %0, " STRINGIFY(csr)
", %1" \
: "=r" (__rcv) : "rK" (__rcv) \
: "memory"); \
__rcv; \
})
◆ csr_read_set
#define csr_read_set |
( |
| csr, |
|
|
| val ) |
Value:({ \
unsigned long __rsv = (unsigned long)(val); \
__asm__
volatile (
"csrrs %0, " STRINGIFY(csr)
", %1" \
: "=r" (__rsv) : "rK" (__rsv) \
: "memory"); \
__rsv; \
})
◆ csr_set
#define csr_set |
( |
| csr, |
|
|
| val ) |
Value:({ \
unsigned long __sv = (unsigned long)(val); \
__asm__
volatile (
"csrs " STRINGIFY(csr)
", %0" \
: : "rK" (__sv) \
: "memory"); \
})
◆ csr_write
#define csr_write |
( |
| csr, |
|
|
| val ) |
Value:({ \
unsigned long __wv = (unsigned long)(val); \
__asm__
volatile (
"csrw " STRINGIFY(csr)
", %0" \
: : "rK" (__wv) \
: "memory"); \
})
◆ DCSR_CAUSE
#define DCSR_CAUSE (7<<6) |
◆ DCSR_CAUSE_DEBUGINT
#define DCSR_CAUSE_DEBUGINT 3 |
◆ DCSR_CAUSE_HALT
#define DCSR_CAUSE_HALT 5 |
◆ DCSR_CAUSE_HWBP
#define DCSR_CAUSE_HWBP 2 |
◆ DCSR_CAUSE_NONE
#define DCSR_CAUSE_NONE 0 |
◆ DCSR_CAUSE_STEP
#define DCSR_CAUSE_STEP 4 |
◆ DCSR_CAUSE_SWBP
#define DCSR_CAUSE_SWBP 1 |
◆ DCSR_DEBUGINT
#define DCSR_DEBUGINT (1<<5) |
◆ DCSR_EBREAKH
#define DCSR_EBREAKH (1<<14) |
◆ DCSR_EBREAKM
#define DCSR_EBREAKM (1<<15) |
◆ DCSR_EBREAKS
#define DCSR_EBREAKS (1<<13) |
◆ DCSR_EBREAKU
#define DCSR_EBREAKU (1<<12) |
◆ DCSR_FULLRESET
#define DCSR_FULLRESET (1<<28) |
◆ DCSR_HALT
◆ DCSR_NDRESET
#define DCSR_NDRESET (1<<29) |
◆ DCSR_PRV
◆ DCSR_STEP
◆ DCSR_STOPCYCLE
#define DCSR_STOPCYCLE (1<<10) |
◆ DCSR_STOPTIME
#define DCSR_STOPTIME (1<<9) |
◆ DCSR_XDEBUGVER
#define DCSR_XDEBUGVER (3U<<30) |
◆ DEFAULT_RSTVEC
#define DEFAULT_RSTVEC 0x00001000 |
◆ DRAM_BASE
#define DRAM_BASE 0x80000000 |
◆ EXT_IO_BASE
#define EXT_IO_BASE 0x40000000 |
◆ INSERT_FIELD
#define INSERT_FIELD |
( |
| val, |
|
|
| which, |
|
|
| fieldval ) |
Value:( \
((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))) \
) \
◆ IRQ_COP
◆ IRQ_H_EXT
◆ IRQ_H_SOFT
◆ IRQ_H_TIMER
◆ IRQ_HOST
◆ IRQ_M_EXT
◆ IRQ_M_SOFT
◆ IRQ_M_TIMER
◆ IRQ_S_EXT
◆ IRQ_S_SOFT
◆ IRQ_S_TIMER
◆ MCONTROL_ACTION
#define MCONTROL_ACTION (0x3f<<12) |
◆ MCONTROL_ACTION_DEBUG_EXCEPTION
#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 |
◆ MCONTROL_ACTION_DEBUG_MODE
#define MCONTROL_ACTION_DEBUG_MODE 1 |
◆ MCONTROL_ACTION_TRACE_EMIT
#define MCONTROL_ACTION_TRACE_EMIT 4 |
◆ MCONTROL_ACTION_TRACE_START
#define MCONTROL_ACTION_TRACE_START 2 |
◆ MCONTROL_ACTION_TRACE_STOP
#define MCONTROL_ACTION_TRACE_STOP 3 |
◆ MCONTROL_CHAIN
#define MCONTROL_CHAIN (1<<11) |
◆ MCONTROL_DMODE
#define MCONTROL_DMODE |
( |
| xlen | ) |
|
◆ MCONTROL_EXECUTE
#define MCONTROL_EXECUTE (1<<2) |
◆ MCONTROL_H
#define MCONTROL_H (1<<5) |
◆ MCONTROL_LOAD
#define MCONTROL_LOAD (1<<0) |
◆ MCONTROL_M
#define MCONTROL_M (1<<6) |
◆ MCONTROL_MASKMAX
#define MCONTROL_MASKMAX |
( |
| xlen | ) |
|
◆ MCONTROL_MATCH
#define MCONTROL_MATCH (0xf<<7) |
◆ MCONTROL_MATCH_EQUAL
#define MCONTROL_MATCH_EQUAL 0 |
◆ MCONTROL_MATCH_GE
#define MCONTROL_MATCH_GE 2 |
◆ MCONTROL_MATCH_LT
#define MCONTROL_MATCH_LT 3 |
◆ MCONTROL_MATCH_MASK_HIGH
#define MCONTROL_MATCH_MASK_HIGH 5 |
◆ MCONTROL_MATCH_MASK_LOW
#define MCONTROL_MATCH_MASK_LOW 4 |
◆ MCONTROL_MATCH_NAPOT
#define MCONTROL_MATCH_NAPOT 1 |
◆ MCONTROL_S
#define MCONTROL_S (1<<4) |
◆ MCONTROL_SELECT
#define MCONTROL_SELECT (1<<19) |
◆ MCONTROL_STORE
#define MCONTROL_STORE (1<<1) |
◆ MCONTROL_TIMING
#define MCONTROL_TIMING (1<<18) |
◆ MCONTROL_TYPE
#define MCONTROL_TYPE |
( |
| xlen | ) |
|
◆ MCONTROL_TYPE_MATCH
#define MCONTROL_TYPE_MATCH 2 |
◆ MCONTROL_TYPE_NONE
#define MCONTROL_TYPE_NONE 0 |
◆ MCONTROL_U
#define MCONTROL_U (1<<3) |
◆ MIP_HEIP
◆ MIP_HSIP
◆ MIP_HTIP
◆ MIP_MEIP
◆ MIP_MSIP
◆ MIP_MTIP
◆ MIP_SEIP
◆ MIP_SSIP
◆ MIP_STIP
◆ MSTATUS32_SD
#define MSTATUS32_SD 0x80000000 |
◆ MSTATUS64_SD
#define MSTATUS64_SD 0x8000000000000000 |
◆ MSTATUS_FS
#define MSTATUS_FS 0x00006000 |
◆ MSTATUS_HIE
#define MSTATUS_HIE 0x00000004 |
◆ MSTATUS_HPIE
#define MSTATUS_HPIE 0x00000040 |
◆ MSTATUS_HPP
#define MSTATUS_HPP 0x00000600 |
◆ MSTATUS_MIE
#define MSTATUS_MIE 0x00000008 |
◆ MSTATUS_MPIE
#define MSTATUS_MPIE 0x00000080 |
◆ MSTATUS_MPP
#define MSTATUS_MPP 0x00001800 |
◆ MSTATUS_MPRV
#define MSTATUS_MPRV 0x00020000 |
◆ MSTATUS_MXR
#define MSTATUS_MXR 0x00080000 |
◆ MSTATUS_SIE
#define MSTATUS_SIE 0x00000002 |
◆ MSTATUS_SPIE
#define MSTATUS_SPIE 0x00000020 |
◆ MSTATUS_SPP
#define MSTATUS_SPP 0x00000100 |
◆ MSTATUS_SUM
#define MSTATUS_SUM 0x00040000 |
◆ MSTATUS_SXL
#define MSTATUS_SXL 0x0000000C00000000 |
◆ MSTATUS_TSR
#define MSTATUS_TSR 0x00400000 |
◆ MSTATUS_TVM
#define MSTATUS_TVM 0x00100000 |
◆ MSTATUS_TW
#define MSTATUS_TW 0x00200000 |
◆ MSTATUS_UIE
#define MSTATUS_UIE 0x00000001 |
◆ MSTATUS_UPIE
#define MSTATUS_UPIE 0x00000010 |
◆ MSTATUS_UXL
#define MSTATUS_UXL 0x0000000300000000 |
◆ MSTATUS_XS
#define MSTATUS_XS 0x00018000 |
◆ PMP_A
◆ PMP_L
◆ PMP_NA4
◆ PMP_NAPOT
◆ PMP_R
◆ PMP_SHIFT
◆ PMP_TOR
◆ PMP_W
◆ PMP_X
◆ PRV_H
◆ PRV_M
◆ PRV_S
◆ PRV_U
◆ PTE_A
#define PTE_A 0x040 /* Accessed */ |
◆ PTE_D
#define PTE_D 0x080 /* Dirty */ |
◆ PTE_G
#define PTE_G 0x020 /* Global */ |
◆ PTE_PPN_SHIFT
◆ PTE_R
#define PTE_R 0x002 /* Read */ |
◆ PTE_SOFT
#define PTE_SOFT 0x300 /* Reserved for Software */ |
◆ PTE_TABLE
Value:
#define PTE_W
Definition csr.h:168
#define PTE_R
Definition csr.h:167
#define PTE_V
Definition csr.h:166
#define PTE_X
Definition csr.h:169
◆ PTE_U
#define PTE_U 0x010 /* User */ |
◆ PTE_V
#define PTE_V 0x001 /* Valid */ |
◆ PTE_W
#define PTE_W 0x004 /* Write */ |
◆ PTE_X
#define PTE_X 0x008 /* Execute */ |
◆ SATP32_ASID
#define SATP32_ASID 0x7FC00000 |
◆ SATP32_MODE
#define SATP32_MODE 0x80000000 |
◆ SATP32_PPN
#define SATP32_PPN 0x003FFFFF |
◆ SATP64_ASID
#define SATP64_ASID 0x0FFFF00000000000 |
◆ SATP64_MODE
#define SATP64_MODE 0xF000000000000000 |
◆ SATP64_PPN
#define SATP64_PPN 0x00000FFFFFFFFFFF |
◆ SATP_MODE_OFF
◆ SATP_MODE_SV32
◆ SATP_MODE_SV39
◆ SATP_MODE_SV48
◆ SATP_MODE_SV57
#define SATP_MODE_SV57 10 |
◆ SATP_MODE_SV64
#define SATP_MODE_SV64 11 |
◆ SIP_SSIP
◆ SIP_STIP
◆ SSTATUS32_SD
#define SSTATUS32_SD 0x80000000 |
◆ SSTATUS64_SD
#define SSTATUS64_SD 0x8000000000000000 |
◆ SSTATUS_FS
#define SSTATUS_FS 0x00006000 |
◆ SSTATUS_MXR
#define SSTATUS_MXR 0x00080000 |
◆ SSTATUS_SIE
#define SSTATUS_SIE 0x00000002 |
◆ SSTATUS_SPIE
#define SSTATUS_SPIE 0x00000020 |
◆ SSTATUS_SPP
#define SSTATUS_SPP 0x00000100 |
◆ SSTATUS_SUM
#define SSTATUS_SUM 0x00040000 |
◆ SSTATUS_UIE
#define SSTATUS_UIE 0x00000001 |
◆ SSTATUS_UPIE
#define SSTATUS_UPIE 0x00000010 |
◆ SSTATUS_UXL
#define SSTATUS_UXL 0x0000000300000000 |
◆ SSTATUS_XS
#define SSTATUS_XS 0x00018000 |