Zephyr API Documentation  3.6.99
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intel_vtd.h File Reference

Go to the source code of this file.

Macros

#define VTD_VER_REG   0x000 /* Version */
 
#define VTD_CAP_REG   0x008 /* Capability */
 
#define VTD_ECAP_REG   0x010 /* Extended Capability */
 
#define VTD_GCMD_REG   0x018 /* Global Command */
 
#define VTD_GSTS_REG   0x01C /* Global Status */
 
#define VTD_RTADDR_REG   0x020 /* Root Table Address */
 
#define VTD_CCMD_REG   0x028 /* Context Command */
 
#define VTD_FSTS_REG   0x034 /* Fault Status */
 
#define VTD_FECTL_REG   0x038 /* Fault Event Control */
 
#define VTD_FEDATA_REG   0x03C /* Fault Event Data */
 
#define VTD_FEADDR_REG   0x040 /* Fault Event Address */
 
#define VTD_FEUADDR_REG   0x044 /* Fault Event Upper Address */
 
#define VTD_AFLOG_REG   0x058 /* Advanced Fault Log */
 
#define VTD_PMEN_REG   0x064 /* Protected Memory Enable */
 
#define VTD_PLMBASE_REG   0x068 /* Protected Low Memory Base */
 
#define VTD_PLMLIMIT_REG   0x06C /* Protected Low Memory Limit */
 
#define VTD_PHMBASE_REG   0x070 /* Protected High Memory Base */
 
#define VTD_PHMLIMIT_REG   0x078 /* Protected High Memory Limit */
 
#define VTD_IQH_REG   0x080 /* Invalidation Queue Head */
 
#define VTD_IQT_REG   0x088 /* Invalidation Queue Tail */
 
#define VTD_IQA_REG   0x090 /* Invalidation Queue Address */
 
#define VTD_ICS_REG   0x09C /* Invalidation Completion Status */
 
#define VTD_IECTL_REG   0x0A0 /* Invalidation Completion Event Control */
 
#define VTD_IEDATA_REG   0x0A4 /* Invalidation Completion Event Data */
 
#define VTD_IEADDR_REG   0x0A8 /* Invalidation Completion Event Address */
 
#define VTD_IEUADDR_REG   0x0AC /* Invalidation Completion Event Upper Address */
 
#define VTD_IQERCD_REG   0x0B0 /* Invalidation Queue Error Record */
 
#define VTD_IRTA_REG   0x0B8 /* Interrupt Remapping Table Address */
 
#define VTD_PQH_REG   0x0C0 /* Page Request Queue Head */
 
#define VTD_PQT_REG   0x0C8 /* Page Request Queue Tail */
 
#define VTD_PQA_REG   0x0D0 /* Page Request Queue Address */
 
#define VTD_PRS_REG   0x0DC /* Page Request Status */
 
#define VTD_PECTL_REG   0x0E0 /* Page Request Event Control */
 
#define VTD_PEDATA_REG   0x0E4 /* Page Request Event Data */
 
#define VTD_PEADDR_REG   0x0E8 /* Page Request Event Address */
 
#define VTD_PEUADDR_REG   0x0EC /* Page Request Event Upper Address */
 
#define VTD_MTRRCAP_REG   0x100 /* MTRR Capability */
 
#define VTD_MTRRDEF_REG   0x108 /* MTRR Default Type */
 
#define VTD_MTRR_FIX64K_00000_REG   0x120 /* Fixed-range MTRR for 64K_00000 */
 
#define VTD_MTRR_FIX16K_80000_REG   0x128 /* Fixed-range MTRR for 16K_80000 */
 
#define VTD_MTRR_FIX16K_A0000_REG   0x130 /* Fixed-range MTRR for 16K_A0000 */
 
#define VTD_MTRR_FIX4K_C0000_REG   0x138 /* Fixed-range MTRR for 4K_C0000 */
 
#define VTD_MTRR_FIX4K_C8000_REG   0x140 /* Fixed-range MTRR for 4K_C8000 */
 
#define VTD_MTRR_FIX4K_D0000_REG   0x148 /* Fixed-range MTRR for 4K_D0000 */
 
#define VTD_MTRR_FIX4K_D8000_REG   0x150 /* Fixed-range MTRR for 4K_D8000 */
 
#define VTD_MTRR_FIX4K_E0000_REG   0x158 /* Fixed-range MTRR for 4K_E0000 */
 
#define VTD_MTRR_FIX4K_E8000_REG   0x160 /* Fixed-range MTRR for 4K_E8000 */
 
#define VTD_MTRR_FIX4K_F0000_REG   0x168 /* Fixed-range MTRR for 4K_F0000 */
 
#define VTD_MTRR_FIX4K_F8000_REG   0x170 /* Fixed-range MTRR for 4K_F8000 */
 
#define VTD_MTRR_PHYSBASE0_REG   0x180 /* Variable-range MTRR Base0 */
 
#define VTD_MTRR_PHYSMASK0_REG   0x188 /* Variable-range MTRR Mask0 */
 
#define VTD_MTRR_PHYSBASE1_REG   0x190 /* Variable-range MTRR Base1 */
 
#define VTD_MTRR_PHYSMASK1_REG   0x198 /* Variable-range MTRR Mask1 */
 
#define VTD_MTRR_PHYSBASE2_REG   0x1A0 /* Variable-range MTRR Base2 */
 
#define VTD_MTRR_PHYSMASK2_REG   0x1A8 /* Variable-range MTRR Mask2 */
 
#define VTD_MTRR_PHYSBASE3_REG   0x1B0 /* Variable-range MTRR Base3 */
 
#define VTD_MTRR_PHYSMASK3_REG   0x1B8 /* Variable-range MTRR Mask3 */
 
#define VTD_MTRR_PHYSBASE4_REG   0x1C0 /* Variable-range MTRR Base4 */
 
#define VTD_MTRR_PHYSMASK4_REG   0x1C8 /* Variable-range MTRR Mask4 */
 
#define VTD_MTRR_PHYSBASE5_REG   0x1D0 /* Variable-range MTRR Base5 */
 
#define VTD_MTRR_PHYSMASK5_REG   0x1D8 /* Variable-range MTRR Mask5 */
 
#define VTD_MTRR_PHYSBASE6_REG   0x1E0 /* Variable-range MTRR Base6 */
 
#define VTD_MTRR_PHYSMASK6_REG   0x1E8 /* Variable-range MTRR Mask6 */
 
#define VTD_MTRR_PHYSBASE7_REG   0x1F0 /* Variable-range MTRR Base7 */
 
#define VTD_MTRR_PHYSMASK7_REG   0x1F8 /* Variable-range MTRR Mask7 */
 
#define VTD_MTRR_PHYSBASE8_REG   0x200 /* Variable-range MTRR Base8 */
 
#define VTD_MTRR_PHYSMASK8_REG   0x208 /* Variable-range MTRR Mask8 */
 
#define VTD_MTRR_PHYSBASE9_REG   0x210 /* Variable-range MTRR Base9 */
 
#define VTD_MTRR_PHYSMASK9_REG   0x218 /* Variable-range MTRR Mask9 */
 
#define VTD_VCCAP_REG   0xE00 /* Virtual Command Capability */
 
#define VTD_VCMD   0xE10 /* Virtual Command */
 
#define VTD_VCRSP   0xE20 /* Virtual Command Response */
 
#define VTD_CAP_NFR_POS   40
 
#define VTD_CAP_NFR_MASK   ((uint64_t)0xFFUL << VTD_CAP_NFR_POS)
 
#define VTD_CAP_NFR(cap)    (((uint64_t)cap & VTD_CAP_NFR_MASK) >> VTD_CAP_NFR_POS)
 
#define VTD_CAP_FRO_POS   24
 
#define VTD_CAP_FRO_MASK   ((uint64_t)0x3FFUL << VTD_CAP_FRO_POS)
 
#define VTD_CAP_FRO(cap)    (((uint64_t)cap & VTD_CAP_FRO_MASK) >> VTD_CAP_FRO_POS)
 
#define VTD_ECAP_C   BIT(0)
 
#define VTD_GCMD_CFI   23
 
#define VTD_GCMD_SIRTP   24
 
#define VTD_GCMD_IRE   25
 
#define VTD_GCMD_QIE   26
 
#define VTD_GCMD_WBF   27
 
#define VTD_GCMD_EAFL   28
 
#define VTD_GCMD_SFL   29
 
#define VTD_GCMD_SRTP   30
 
#define VTD_GCMD_TE   31
 
#define VTD_GSTS_CFIS   23
 
#define VTD_GSTS_SIRTPS   24
 
#define VTD_GSTS_IRES   25
 
#define VTD_GSTS_QIES   26
 
#define VTD_GSTS_WBFS   27
 
#define VTD_GSTS_EAFLS   28
 
#define VTD_GSTS_SFLS   29
 
#define VTD_GSTS_SRTPS   30
 
#define VTD_GSTS_TES   31
 
#define VTD_IRTA_SIZE_MASK   0x000000000000000FUL
 
#define VTD_IRTA_EIME   BIT(11)
 
#define VTD_IRTA_REG_GEN_CONTENT(addr, size, mode)    ((uint64_t)(addr) | (mode) | (size & VTD_IRTA_SIZE_MASK))
 
#define VTD_FECTL_REG_IP   30
 
#define VTD_FECTL_REG_IM   31
 
#define VTD_FSTS_PFO   BIT(0)
 
#define VTD_FSTS_PPF   BIT(1)
 
#define VTD_FSTS_AFO   BIT(2)
 
#define VTD_FSTS_APF   BIT(3)
 
#define VTD_FSTS_IQE   BIT(4)
 
#define VTD_FSTS_ICE   BIT(5)
 
#define VTD_FSTS_ITE   BIT(6)
 
#define VTD_FSTS_FRI_POS   8
 
#define VTD_FSTS_FRI_MASK   (0xF << VTD_FSTS_FRI_POS)
 
#define VTD_FSTS_FRI(status)    ((status & VTD_FSTS_FRI_MASK) >> VTD_FSTS_FRI_POS)
 
#define VTD_FSTS_CLEAR_STATUS
 
#define VTD_FSTS_CLEAR(status)    (status & VTD_FSTS_CLEAR_STATUS)
 
#define VTD_FRCD_REG_SIZE   16
 
#define VTD_FRCD_F   BIT(63)
 
#define VTD_FRCD_T   BIT(62)
 
#define VTD_FRCD_FR_POS   32
 
#define VTD_FRCD_FR_MASK   ((uint64_t)0xFF << VTD_FRCD_FR_POS)
 
#define VTD_FRCD_FR(fault)    ((uint8_t)((fault & VTD_FRCD_FR_MASK) >> VTD_FRCD_FR_POS))
 
#define VTD_FRCD_SID_MASK   0xFFFF
 
#define VTD_FRCD_SID(fault)    ((uint16_t)(fault & VTD_FRCD_SID_MASK))
 
#define VTD_FRCD_FI_POS   12
 
#define VTD_FRCD_FI_MASK   ((uint64_t)0xFFFFFFFFFFFFF << VTD_FRCD_FI_POS)
 
#define VTD_FRCD_FI(fault)    ((fault & VTD_FRCD_FI_MASK) >> VTD_FRCD_FI_POS)
 
#define VTD_FRCD_FI_IR_POS   48
 
#define VTD_FRCD_FI_IR_MASK   ((uint64_t)0xFFFF << VTD_FRCD_FI_IR_POS)
 
#define VTD_FRCD_FI_IR(fault)    ((fault & VTD_FRCD_FI_IR_MASK) >> VTD_FRCD_FI_IR_POS)
 
#define VTD_IQA_SIZE_MASK   0x7
 
#define VTD_IQA_WIDTH_128_BIT   0
 
#define VTD_IQA_WIDTH_256_BIT   BIT(11)
 
#define VTD_IQA_REG_GEN_CONTENT(addr, width, size)    ((uint64_t)0 | (addr) | (width) | (size & VTD_IQA_SIZE_MASK))
 
#define VTD_IQH_QH_POS_128   4
 
#define VTD_IQH_QH_MASK   ((uint64_t)0xEF << VTD_IQH_QH_POS_128)
 
#define VTD_IQT_QT_POS_128   4
 
#define VTD_IQT_QT_MASK   ((uint64_t)0xEF << VTD_IQT_QT_POS_128)
 

Macro Definition Documentation

◆ VTD_AFLOG_REG

#define VTD_AFLOG_REG   0x058 /* Advanced Fault Log */

◆ VTD_CAP_FRO

#define VTD_CAP_FRO (   cap)     (((uint64_t)cap & VTD_CAP_FRO_MASK) >> VTD_CAP_FRO_POS)

◆ VTD_CAP_FRO_MASK

#define VTD_CAP_FRO_MASK   ((uint64_t)0x3FFUL << VTD_CAP_FRO_POS)

◆ VTD_CAP_FRO_POS

#define VTD_CAP_FRO_POS   24

◆ VTD_CAP_NFR

#define VTD_CAP_NFR (   cap)     (((uint64_t)cap & VTD_CAP_NFR_MASK) >> VTD_CAP_NFR_POS)

◆ VTD_CAP_NFR_MASK

#define VTD_CAP_NFR_MASK   ((uint64_t)0xFFUL << VTD_CAP_NFR_POS)

◆ VTD_CAP_NFR_POS

#define VTD_CAP_NFR_POS   40

◆ VTD_CAP_REG

#define VTD_CAP_REG   0x008 /* Capability */

◆ VTD_CCMD_REG

#define VTD_CCMD_REG   0x028 /* Context Command */

◆ VTD_ECAP_C

#define VTD_ECAP_C   BIT(0)

◆ VTD_ECAP_REG

#define VTD_ECAP_REG   0x010 /* Extended Capability */

◆ VTD_FEADDR_REG

#define VTD_FEADDR_REG   0x040 /* Fault Event Address */

◆ VTD_FECTL_REG

#define VTD_FECTL_REG   0x038 /* Fault Event Control */

◆ VTD_FECTL_REG_IM

#define VTD_FECTL_REG_IM   31

◆ VTD_FECTL_REG_IP

#define VTD_FECTL_REG_IP   30

◆ VTD_FEDATA_REG

#define VTD_FEDATA_REG   0x03C /* Fault Event Data */

◆ VTD_FEUADDR_REG

#define VTD_FEUADDR_REG   0x044 /* Fault Event Upper Address */

◆ VTD_FRCD_F

#define VTD_FRCD_F   BIT(63)

◆ VTD_FRCD_FI

#define VTD_FRCD_FI (   fault)     ((fault & VTD_FRCD_FI_MASK) >> VTD_FRCD_FI_POS)

◆ VTD_FRCD_FI_IR

#define VTD_FRCD_FI_IR (   fault)     ((fault & VTD_FRCD_FI_IR_MASK) >> VTD_FRCD_FI_IR_POS)

◆ VTD_FRCD_FI_IR_MASK

#define VTD_FRCD_FI_IR_MASK   ((uint64_t)0xFFFF << VTD_FRCD_FI_IR_POS)

◆ VTD_FRCD_FI_IR_POS

#define VTD_FRCD_FI_IR_POS   48

◆ VTD_FRCD_FI_MASK

#define VTD_FRCD_FI_MASK   ((uint64_t)0xFFFFFFFFFFFFF << VTD_FRCD_FI_POS)

◆ VTD_FRCD_FI_POS

#define VTD_FRCD_FI_POS   12

◆ VTD_FRCD_FR

#define VTD_FRCD_FR (   fault)     ((uint8_t)((fault & VTD_FRCD_FR_MASK) >> VTD_FRCD_FR_POS))

◆ VTD_FRCD_FR_MASK

#define VTD_FRCD_FR_MASK   ((uint64_t)0xFF << VTD_FRCD_FR_POS)

◆ VTD_FRCD_FR_POS

#define VTD_FRCD_FR_POS   32

◆ VTD_FRCD_REG_SIZE

#define VTD_FRCD_REG_SIZE   16

◆ VTD_FRCD_SID

#define VTD_FRCD_SID (   fault)     ((uint16_t)(fault & VTD_FRCD_SID_MASK))

◆ VTD_FRCD_SID_MASK

#define VTD_FRCD_SID_MASK   0xFFFF

◆ VTD_FRCD_T

#define VTD_FRCD_T   BIT(62)

◆ VTD_FSTS_AFO

#define VTD_FSTS_AFO   BIT(2)

◆ VTD_FSTS_APF

#define VTD_FSTS_APF   BIT(3)

◆ VTD_FSTS_CLEAR

#define VTD_FSTS_CLEAR (   status)     (status & VTD_FSTS_CLEAR_STATUS)

◆ VTD_FSTS_CLEAR_STATUS

#define VTD_FSTS_CLEAR_STATUS
Value:
#define VTD_FSTS_IQE
Definition: intel_vtd.h:140
#define VTD_FSTS_APF
Definition: intel_vtd.h:139
#define VTD_FSTS_ICE
Definition: intel_vtd.h:141
#define VTD_FSTS_PFO
Definition: intel_vtd.h:136
#define VTD_FSTS_ITE
Definition: intel_vtd.h:142
#define VTD_FSTS_AFO
Definition: intel_vtd.h:138

◆ VTD_FSTS_FRI

#define VTD_FSTS_FRI (   status)     ((status & VTD_FSTS_FRI_MASK) >> VTD_FSTS_FRI_POS)

◆ VTD_FSTS_FRI_MASK

#define VTD_FSTS_FRI_MASK   (0xF << VTD_FSTS_FRI_POS)

◆ VTD_FSTS_FRI_POS

#define VTD_FSTS_FRI_POS   8

◆ VTD_FSTS_ICE

#define VTD_FSTS_ICE   BIT(5)

◆ VTD_FSTS_IQE

#define VTD_FSTS_IQE   BIT(4)

◆ VTD_FSTS_ITE

#define VTD_FSTS_ITE   BIT(6)

◆ VTD_FSTS_PFO

#define VTD_FSTS_PFO   BIT(0)

◆ VTD_FSTS_PPF

#define VTD_FSTS_PPF   BIT(1)

◆ VTD_FSTS_REG

#define VTD_FSTS_REG   0x034 /* Fault Status */

◆ VTD_GCMD_CFI

#define VTD_GCMD_CFI   23

◆ VTD_GCMD_EAFL

#define VTD_GCMD_EAFL   28

◆ VTD_GCMD_IRE

#define VTD_GCMD_IRE   25

◆ VTD_GCMD_QIE

#define VTD_GCMD_QIE   26

◆ VTD_GCMD_REG

#define VTD_GCMD_REG   0x018 /* Global Command */

◆ VTD_GCMD_SFL

#define VTD_GCMD_SFL   29

◆ VTD_GCMD_SIRTP

#define VTD_GCMD_SIRTP   24

◆ VTD_GCMD_SRTP

#define VTD_GCMD_SRTP   30

◆ VTD_GCMD_TE

#define VTD_GCMD_TE   31

◆ VTD_GCMD_WBF

#define VTD_GCMD_WBF   27

◆ VTD_GSTS_CFIS

#define VTD_GSTS_CFIS   23

◆ VTD_GSTS_EAFLS

#define VTD_GSTS_EAFLS   28

◆ VTD_GSTS_IRES

#define VTD_GSTS_IRES   25

◆ VTD_GSTS_QIES

#define VTD_GSTS_QIES   26

◆ VTD_GSTS_REG

#define VTD_GSTS_REG   0x01C /* Global Status */

◆ VTD_GSTS_SFLS

#define VTD_GSTS_SFLS   29

◆ VTD_GSTS_SIRTPS

#define VTD_GSTS_SIRTPS   24

◆ VTD_GSTS_SRTPS

#define VTD_GSTS_SRTPS   30

◆ VTD_GSTS_TES

#define VTD_GSTS_TES   31

◆ VTD_GSTS_WBFS

#define VTD_GSTS_WBFS   27

◆ VTD_ICS_REG

#define VTD_ICS_REG   0x09C /* Invalidation Completion Status */

◆ VTD_IEADDR_REG

#define VTD_IEADDR_REG   0x0A8 /* Invalidation Completion Event Address */

◆ VTD_IECTL_REG

#define VTD_IECTL_REG   0x0A0 /* Invalidation Completion Event Control */

◆ VTD_IEDATA_REG

#define VTD_IEDATA_REG   0x0A4 /* Invalidation Completion Event Data */

◆ VTD_IEUADDR_REG

#define VTD_IEUADDR_REG   0x0AC /* Invalidation Completion Event Upper Address */

◆ VTD_IQA_REG

#define VTD_IQA_REG   0x090 /* Invalidation Queue Address */

◆ VTD_IQA_REG_GEN_CONTENT

#define VTD_IQA_REG_GEN_CONTENT (   addr,
  width,
  size 
)     ((uint64_t)0 | (addr) | (width) | (size & VTD_IQA_SIZE_MASK))

◆ VTD_IQA_SIZE_MASK

#define VTD_IQA_SIZE_MASK   0x7

◆ VTD_IQA_WIDTH_128_BIT

#define VTD_IQA_WIDTH_128_BIT   0

◆ VTD_IQA_WIDTH_256_BIT

#define VTD_IQA_WIDTH_256_BIT   BIT(11)

◆ VTD_IQERCD_REG

#define VTD_IQERCD_REG   0x0B0 /* Invalidation Queue Error Record */

◆ VTD_IQH_QH_MASK

#define VTD_IQH_QH_MASK   ((uint64_t)0xEF << VTD_IQH_QH_POS_128)

◆ VTD_IQH_QH_POS_128

#define VTD_IQH_QH_POS_128   4

◆ VTD_IQH_REG

#define VTD_IQH_REG   0x080 /* Invalidation Queue Head */

◆ VTD_IQT_QT_MASK

#define VTD_IQT_QT_MASK   ((uint64_t)0xEF << VTD_IQT_QT_POS_128)

◆ VTD_IQT_QT_POS_128

#define VTD_IQT_QT_POS_128   4

◆ VTD_IQT_REG

#define VTD_IQT_REG   0x088 /* Invalidation Queue Tail */

◆ VTD_IRTA_EIME

#define VTD_IRTA_EIME   BIT(11)

◆ VTD_IRTA_REG

#define VTD_IRTA_REG   0x0B8 /* Interrupt Remapping Table Address */

◆ VTD_IRTA_REG_GEN_CONTENT

#define VTD_IRTA_REG_GEN_CONTENT (   addr,
  size,
  mode 
)     ((uint64_t)(addr) | (mode) | (size & VTD_IRTA_SIZE_MASK))

◆ VTD_IRTA_SIZE_MASK

#define VTD_IRTA_SIZE_MASK   0x000000000000000FUL

◆ VTD_MTRR_FIX16K_80000_REG

#define VTD_MTRR_FIX16K_80000_REG   0x128 /* Fixed-range MTRR for 16K_80000 */

◆ VTD_MTRR_FIX16K_A0000_REG

#define VTD_MTRR_FIX16K_A0000_REG   0x130 /* Fixed-range MTRR for 16K_A0000 */

◆ VTD_MTRR_FIX4K_C0000_REG

#define VTD_MTRR_FIX4K_C0000_REG   0x138 /* Fixed-range MTRR for 4K_C0000 */

◆ VTD_MTRR_FIX4K_C8000_REG

#define VTD_MTRR_FIX4K_C8000_REG   0x140 /* Fixed-range MTRR for 4K_C8000 */

◆ VTD_MTRR_FIX4K_D0000_REG

#define VTD_MTRR_FIX4K_D0000_REG   0x148 /* Fixed-range MTRR for 4K_D0000 */

◆ VTD_MTRR_FIX4K_D8000_REG

#define VTD_MTRR_FIX4K_D8000_REG   0x150 /* Fixed-range MTRR for 4K_D8000 */

◆ VTD_MTRR_FIX4K_E0000_REG

#define VTD_MTRR_FIX4K_E0000_REG   0x158 /* Fixed-range MTRR for 4K_E0000 */

◆ VTD_MTRR_FIX4K_E8000_REG

#define VTD_MTRR_FIX4K_E8000_REG   0x160 /* Fixed-range MTRR for 4K_E8000 */

◆ VTD_MTRR_FIX4K_F0000_REG

#define VTD_MTRR_FIX4K_F0000_REG   0x168 /* Fixed-range MTRR for 4K_F0000 */

◆ VTD_MTRR_FIX4K_F8000_REG

#define VTD_MTRR_FIX4K_F8000_REG   0x170 /* Fixed-range MTRR for 4K_F8000 */

◆ VTD_MTRR_FIX64K_00000_REG

#define VTD_MTRR_FIX64K_00000_REG   0x120 /* Fixed-range MTRR for 64K_00000 */

◆ VTD_MTRR_PHYSBASE0_REG

#define VTD_MTRR_PHYSBASE0_REG   0x180 /* Variable-range MTRR Base0 */

◆ VTD_MTRR_PHYSBASE1_REG

#define VTD_MTRR_PHYSBASE1_REG   0x190 /* Variable-range MTRR Base1 */

◆ VTD_MTRR_PHYSBASE2_REG

#define VTD_MTRR_PHYSBASE2_REG   0x1A0 /* Variable-range MTRR Base2 */

◆ VTD_MTRR_PHYSBASE3_REG

#define VTD_MTRR_PHYSBASE3_REG   0x1B0 /* Variable-range MTRR Base3 */

◆ VTD_MTRR_PHYSBASE4_REG

#define VTD_MTRR_PHYSBASE4_REG   0x1C0 /* Variable-range MTRR Base4 */

◆ VTD_MTRR_PHYSBASE5_REG

#define VTD_MTRR_PHYSBASE5_REG   0x1D0 /* Variable-range MTRR Base5 */

◆ VTD_MTRR_PHYSBASE6_REG

#define VTD_MTRR_PHYSBASE6_REG   0x1E0 /* Variable-range MTRR Base6 */

◆ VTD_MTRR_PHYSBASE7_REG

#define VTD_MTRR_PHYSBASE7_REG   0x1F0 /* Variable-range MTRR Base7 */

◆ VTD_MTRR_PHYSBASE8_REG

#define VTD_MTRR_PHYSBASE8_REG   0x200 /* Variable-range MTRR Base8 */

◆ VTD_MTRR_PHYSBASE9_REG

#define VTD_MTRR_PHYSBASE9_REG   0x210 /* Variable-range MTRR Base9 */

◆ VTD_MTRR_PHYSMASK0_REG

#define VTD_MTRR_PHYSMASK0_REG   0x188 /* Variable-range MTRR Mask0 */

◆ VTD_MTRR_PHYSMASK1_REG

#define VTD_MTRR_PHYSMASK1_REG   0x198 /* Variable-range MTRR Mask1 */

◆ VTD_MTRR_PHYSMASK2_REG

#define VTD_MTRR_PHYSMASK2_REG   0x1A8 /* Variable-range MTRR Mask2 */

◆ VTD_MTRR_PHYSMASK3_REG

#define VTD_MTRR_PHYSMASK3_REG   0x1B8 /* Variable-range MTRR Mask3 */

◆ VTD_MTRR_PHYSMASK4_REG

#define VTD_MTRR_PHYSMASK4_REG   0x1C8 /* Variable-range MTRR Mask4 */

◆ VTD_MTRR_PHYSMASK5_REG

#define VTD_MTRR_PHYSMASK5_REG   0x1D8 /* Variable-range MTRR Mask5 */

◆ VTD_MTRR_PHYSMASK6_REG

#define VTD_MTRR_PHYSMASK6_REG   0x1E8 /* Variable-range MTRR Mask6 */

◆ VTD_MTRR_PHYSMASK7_REG

#define VTD_MTRR_PHYSMASK7_REG   0x1F8 /* Variable-range MTRR Mask7 */

◆ VTD_MTRR_PHYSMASK8_REG

#define VTD_MTRR_PHYSMASK8_REG   0x208 /* Variable-range MTRR Mask8 */

◆ VTD_MTRR_PHYSMASK9_REG

#define VTD_MTRR_PHYSMASK9_REG   0x218 /* Variable-range MTRR Mask9 */

◆ VTD_MTRRCAP_REG

#define VTD_MTRRCAP_REG   0x100 /* MTRR Capability */

◆ VTD_MTRRDEF_REG

#define VTD_MTRRDEF_REG   0x108 /* MTRR Default Type */

◆ VTD_PEADDR_REG

#define VTD_PEADDR_REG   0x0E8 /* Page Request Event Address */

◆ VTD_PECTL_REG

#define VTD_PECTL_REG   0x0E0 /* Page Request Event Control */

◆ VTD_PEDATA_REG

#define VTD_PEDATA_REG   0x0E4 /* Page Request Event Data */

◆ VTD_PEUADDR_REG

#define VTD_PEUADDR_REG   0x0EC /* Page Request Event Upper Address */

◆ VTD_PHMBASE_REG

#define VTD_PHMBASE_REG   0x070 /* Protected High Memory Base */

◆ VTD_PHMLIMIT_REG

#define VTD_PHMLIMIT_REG   0x078 /* Protected High Memory Limit */

◆ VTD_PLMBASE_REG

#define VTD_PLMBASE_REG   0x068 /* Protected Low Memory Base */

◆ VTD_PLMLIMIT_REG

#define VTD_PLMLIMIT_REG   0x06C /* Protected Low Memory Limit */

◆ VTD_PMEN_REG

#define VTD_PMEN_REG   0x064 /* Protected Memory Enable */

◆ VTD_PQA_REG

#define VTD_PQA_REG   0x0D0 /* Page Request Queue Address */

◆ VTD_PQH_REG

#define VTD_PQH_REG   0x0C0 /* Page Request Queue Head */

◆ VTD_PQT_REG

#define VTD_PQT_REG   0x0C8 /* Page Request Queue Tail */

◆ VTD_PRS_REG

#define VTD_PRS_REG   0x0DC /* Page Request Status */

◆ VTD_RTADDR_REG

#define VTD_RTADDR_REG   0x020 /* Root Table Address */

◆ VTD_VCCAP_REG

#define VTD_VCCAP_REG   0xE00 /* Virtual Command Capability */

◆ VTD_VCMD

#define VTD_VCMD   0xE10 /* Virtual Command */

◆ VTD_VCRSP

#define VTD_VCRSP   0xE20 /* Virtual Command Response */

◆ VTD_VER_REG

#define VTD_VER_REG   0x000 /* Version */