Go to the source code of this file.
◆ CSR_REG
◆ RTC_SEL
◆ STM32_CLOCK
#define STM32_CLOCK |
( |
|
val, |
|
|
|
mask, |
|
|
|
shift, |
|
|
|
reg |
|
) |
| |
Value:
#define STM32_CLOCK_SHIFT_SHIFT
Definition: stm32l1_clock.h:31
#define STM32_CLOCK_REG_SHIFT
Definition: stm32l1_clock.h:29
#define STM32_CLOCK_REG_MASK
Definition: stm32l1_clock.h:28
#define STM32_CLOCK_MASK_MASK
Definition: stm32l1_clock.h:32
#define STM32_CLOCK_VAL_MASK
Definition: stm32l1_clock.h:34
#define STM32_CLOCK_MASK_SHIFT
Definition: stm32l1_clock.h:33
#define STM32_CLOCK_VAL_SHIFT
Definition: stm32l1_clock.h:35
#define STM32_CLOCK_SHIFT_MASK
Definition: stm32l1_clock.h:30
STM32 clock configuration bit field.
- reg (1/2/3) [ 0 : 7 ]
- shift (0..31) [ 8 : 12 ]
- mask (0x1, 0x3, 0x7) [ 13 : 15 ]
- val (0..7) [ 16 : 18 ]
- Parameters
-
reg | RCC_CCIPRx register offset |
shift | Position within RCC_CCIPRx. |
mask | Mask for the RCC_CCIPRx field. |
val | Clock value (0, 1, ... 7). |
◆ STM32_CLOCK_BUS_AHB1
#define STM32_CLOCK_BUS_AHB1 0x01c |
◆ STM32_CLOCK_BUS_APB1
#define STM32_CLOCK_BUS_APB1 0x024 |
◆ STM32_CLOCK_BUS_APB2
#define STM32_CLOCK_BUS_APB2 0x020 |
◆ STM32_CLOCK_MASK_MASK
#define STM32_CLOCK_MASK_MASK 0x7U |
◆ STM32_CLOCK_MASK_SHIFT
#define STM32_CLOCK_MASK_SHIFT 13U |
◆ STM32_CLOCK_REG_MASK
#define STM32_CLOCK_REG_MASK 0xFFU |
◆ STM32_CLOCK_REG_SHIFT
#define STM32_CLOCK_REG_SHIFT 0U |
◆ STM32_CLOCK_SHIFT_MASK
#define STM32_CLOCK_SHIFT_MASK 0x1FU |
◆ STM32_CLOCK_SHIFT_SHIFT
#define STM32_CLOCK_SHIFT_SHIFT 8U |
◆ STM32_CLOCK_VAL_MASK
#define STM32_CLOCK_VAL_MASK 0x7U |
◆ STM32_CLOCK_VAL_SHIFT
#define STM32_CLOCK_VAL_SHIFT 16U |
◆ STM32_PERIPH_BUS_MAX
◆ STM32_PERIPH_BUS_MIN
◆ STM32_SRC_HSE
Domain clocks.
System clock Fixed clocks