stm32f427_clock.h File Reference

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Macros
#define	DCKCFGR_REG   0x8C
	RCC_DCKCFGR register offset.
#define	CKDFSDM2A_SEL(val)   STM32_CLOCK(val, 1, 14, DCKCFGR_REG)
	Device domain clocks selection helpers.
#define	CKDFSDM1A_SEL(val)   STM32_CLOCK(val, 1, 15, DCKCFGR_REG)
#define	SAI1A_SEL(val)   STM32_CLOCK(val, 3, 20, DCKCFGR_REG)
#define	SAI1B_SEL(val)   STM32_CLOCK(val, 3, 22, DCKCFGR_REG)
#define	CLK48M_SEL(val)   STM32_CLOCK(val, 1, 27, DCKCFGR_REG)
#define	SDMMC_SEL(val)   STM32_CLOCK(val, 1, 28, DCKCFGR_REG)
#define	DSI_SEL(val)   STM32_CLOCK(val, 1, 29, DCKCFGR_REG)

Macro Definition Documentation

CKDFSDM1A_SEL

#define CKDFSDM1A_SEL

(

val

)

STM32_CLOCK(val, 1, 15, DCKCFGR_REG)

CKDFSDM2A_SEL

#define CKDFSDM2A_SEL

(

val

)

STM32_CLOCK(val, 1, 14, DCKCFGR_REG)

Device domain clocks selection helpers.

DCKCFGR devices

CLK48M_SEL

#define CLK48M_SEL

(

val

)

STM32_CLOCK(val, 1, 27, DCKCFGR_REG)

DCKCFGR_REG

#define DCKCFGR_REG   0x8C

RCC_DCKCFGR register offset.

DSI_SEL

#define DSI_SEL

(

val

)

STM32_CLOCK(val, 1, 29, DCKCFGR_REG)

SAI1A_SEL

#define SAI1A_SEL

(

val

)

STM32_CLOCK(val, 3, 20, DCKCFGR_REG)

SAI1B_SEL

#define SAI1B_SEL

(

val

)

STM32_CLOCK(val, 3, 22, DCKCFGR_REG)

SDMMC_SEL

#define SDMMC_SEL

(

val

)

STM32_CLOCK(val, 1, 28, DCKCFGR_REG)