PCIe Host Interface. More...

Modules
	PCIe Capabilities

	PCIe Host MSI Interface
	PCIe Host MSI Interface.

	PCIe Host PTM Interface
	PCIe Host PTM Interface.

	PCIe Virtual Channel Host Interface
	PCIe Virtual Channel Host Interface.

Data Structures
struct	pcie_dev

struct	pcie_bar

struct	pcie_scan_opt
	Options for performing a scan for PCI devices. More...

Macros
#define	PCIE_ID_IS_VALID(id)

#define	PCIE_DT_ID(node_id)
	Get the PCIe Vendor and Device ID for a node.

#define	PCIE_DT_INST_ID(inst) PCIE_DT_ID(DT_DRV_INST(inst))
	Get the PCIe Vendor and Device ID for a node.

#define	DEVICE_PCIE_DECLARE(node_id)
	Declare a PCIe context variable for a DTS node.

#define	DEVICE_PCIE_INST_DECLARE(inst) DEVICE_PCIE_DECLARE(DT_DRV_INST(inst))
	Declare a PCIe context variable for a DTS node.

#define	DEVICE_PCIE_INIT(node_id, name) .name = &Z_DEVICE_PCIE_NAME(node_id)
	Initialize a named struct member to point at a PCIe context.

#define	DEVICE_PCIE_INST_INIT(inst, name) DEVICE_PCIE_INIT(DT_DRV_INST(inst), name)
	Initialize a named struct member to point at a PCIe context.

#define	PCIE_HOST_CONTROLLER(n) PCIE_BDF(0, 0, n)
	Get the BDF for a given PCI host controller.

#define	PCIE_CONF_CAPPTR 13U /* capabilities pointer */

#define	PCIE_CONF_CAPPTR_FIRST(w) (((w) >> 2) & 0x3FU)

#define	PCIE_CONF_CAP_ID(w) ((w) & 0xFFU)

#define	PCIE_CONF_CAP_NEXT(w) (((w) >> 10) & 0x3FU)

#define	PCIE_CONF_EXT_CAPPTR 64U

#define	PCIE_CONF_EXT_CAP_ID(w) ((w) & 0xFFFFU)

#define	PCIE_CONF_EXT_CAP_VER(w) (((w) >> 16) & 0xFU)

#define	PCIE_CONF_EXT_CAP_NEXT(w) (((w) >> 20) & 0xFFFU)

#define	PCIE_CONF_ID 0U

#define	PCIE_CONF_CMDSTAT 1U /* command/status register */

#define	PCIE_CONF_CMDSTAT_IO 0x00000001U /* I/O access enable */

#define	PCIE_CONF_CMDSTAT_MEM 0x00000002U /* mem access enable */

#define	PCIE_CONF_CMDSTAT_MASTER 0x00000004U /* bus master enable */

#define	PCIE_CONF_CMDSTAT_INTERRUPT 0x00080000U /* interrupt status */

#define	PCIE_CONF_CMDSTAT_CAPS 0x00100000U /* capabilities list */

#define	PCIE_CONF_CLASSREV 2U /* class/revision register */

#define	PCIE_CONF_CLASSREV_CLASS(w) (((w) >> 24) & 0xFFU)

#define	PCIE_CONF_CLASSREV_SUBCLASS(w) (((w) >> 16) & 0xFFU)

#define	PCIE_CONF_CLASSREV_PROGIF(w) (((w) >> 8) & 0xFFU)

#define	PCIE_CONF_CLASSREV_REV(w) ((w) & 0xFFU)

#define	PCIE_CONF_TYPE 3U

#define	PCIE_CONF_MULTIFUNCTION(w) (((w) & 0x00800000U) != 0U)

#define	PCIE_CONF_TYPE_BRIDGE(w) (((w) & 0x007F0000U) != 0U)

#define	PCIE_CONF_TYPE_GET(w) (((w) >> 16) & 0x7F)

#define	PCIE_CONF_TYPE_STANDARD 0x0U

#define	PCIE_CONF_TYPE_PCI_BRIDGE 0x1U

#define	PCIE_CONF_TYPE_CARDBUS_BRIDGE 0x2U

#define	PCIE_CONF_BAR0 4U

#define	PCIE_CONF_BAR1 5U

#define	PCIE_CONF_BAR2 6U

#define	PCIE_CONF_BAR3 7U

#define	PCIE_CONF_BAR4 8U

#define	PCIE_CONF_BAR5 9U

#define	PCIE_CONF_BAR_IO(w) (((w) & 0x00000001U) == 0x00000001U)

#define	PCIE_CONF_BAR_MEM(w) (((w) & 0x00000001U) != 0x00000001U)

#define	PCIE_CONF_BAR_64(w) (((w) & 0x00000006U) == 0x00000004U)

#define	PCIE_CONF_BAR_ADDR(w) ((w) & ~0xfUL)

#define	PCIE_CONF_BAR_IO_ADDR(w) ((w) & ~0x3UL)

#define	PCIE_CONF_BAR_FLAGS(w) ((w) & 0xfUL)

#define	PCIE_CONF_BAR_NONE 0U

#define	PCIE_CONF_BAR_INVAL 0xFFFFFFF0U

#define	PCIE_CONF_BAR_INVAL64 0xFFFFFFFFFFFFFFF0UL

#define	PCIE_CONF_BAR_INVAL_FLAGS(w)

#define	PCIE_BUS_NUMBER 6U

#define	PCIE_BUS_PRIMARY_NUMBER(w) ((w) & 0xffUL)

#define	PCIE_BUS_SECONDARY_NUMBER(w) (((w) >> 8) & 0xffUL)

#define	PCIE_BUS_SUBORDINATE_NUMBER(w) (((w) >> 16) & 0xffUL)

#define	PCIE_SECONDARY_LATENCY_TIMER(w) (((w) >> 24) & 0xffUL)

#define	PCIE_BUS_NUMBER_VAL(prim, sec, sub, lat)

#define	PCIE_IO_SEC_STATUS 7U

#define	PCIE_IO_BASE(w) ((w) & 0xffUL)

#define	PCIE_IO_LIMIT(w) (((w) >> 8) & 0xffUL)

#define	PCIE_SEC_STATUS(w) (((w) >> 16) & 0xffffUL)

#define	PCIE_IO_SEC_STATUS_VAL(iob, iol, sec_status)

#define	PCIE_MEM_BASE_LIMIT 8U

#define	PCIE_MEM_BASE(w) ((w) & 0xffffUL)

#define	PCIE_MEM_LIMIT(w) (((w) >> 16) & 0xffffUL)

#define	PCIE_MEM_BASE_LIMIT_VAL(memb, meml)

#define	PCIE_PREFETCH_BASE_LIMIT 9U

#define	PCIE_PREFETCH_BASE(w) ((w) & 0xffffUL)

#define	PCIE_PREFETCH_LIMIT(w) (((w) >> 16) & 0xffffUL)

#define	PCIE_PREFETCH_BASE_LIMIT_VAL(pmemb, pmeml)

#define	PCIE_PREFETCH_BASE_UPPER 10U

#define	PCIE_PREFETCH_LIMIT_UPPER 11U

#define	PCIE_IO_BASE_LIMIT_UPPER 12U

#define	PCIE_IO_BASE_UPPER(w) ((w) & 0xffffUL)

#define	PCIE_IO_LIMIT_UPPER(w) (((w) >> 16) & 0xffffUL)

#define	PCIE_IO_BASE_LIMIT_UPPER_VAL(iobu, iolu)

#define	PCIE_CONF_INTR 15U

#define	PCIE_CONF_INTR_IRQ(w) ((w) & 0xFFU)

#define	PCIE_CONF_INTR_IRQ_NONE 0xFFU /* no interrupt routed */

#define	PCIE_MAX_BUS (0xFFFFFFFFU & PCIE_BDF_BUS_MASK)

#define	PCIE_MAX_DEV (0xFFFFFFFFU & PCIE_BDF_DEV_MASK)

#define	PCIE_MAX_FUNC (0xFFFFFFFFU & PCIE_BDF_FUNC_MASK)

#define	PCIE_IRQ_CONNECT(bdf_p, irq_p, priority_p, isr_p, isr_param_p, flags_p)
	Initialize an interrupt handler for a PCIe endpoint IRQ.

Typedefs
typedef uint32_t	pcie_bdf_t
	A unique PCI(e) endpoint (bus, device, function).

typedef uint32_t	pcie_id_t
	A unique PCI(e) identifier (vendor ID, device ID).

typedef bool(*	pcie_scan_cb_t) (pcie_bdf_t bdf, pcie_id_t id, void *cb_data)
	Callback type used for scanning for PCI endpoints.

Enumerations
enum	{ PCIE_SCAN_RECURSIVE = BIT(0) , PCIE_SCAN_CB_ALL = BIT(1) }

Functions
uint32_t	pcie_conf_read (pcie_bdf_t bdf, unsigned int reg)
	Read a 32-bit word from an endpoint's configuration space.

void	pcie_conf_write (pcie_bdf_t bdf, unsigned int reg, uint32_t data)
	Write a 32-bit word to an endpoint's configuration space.

int	pcie_scan (const struct pcie_scan_opt *opt)
	Scan for PCIe devices.

bool	pcie_get_mbar (pcie_bdf_t bdf, unsigned int bar_index, struct pcie_bar *mbar)
	Get the MBAR at a specific BAR index.

bool	pcie_probe_mbar (pcie_bdf_t bdf, unsigned int index, struct pcie_bar *mbar)
	Probe the nth MMIO address assigned to an endpoint.

bool	pcie_get_iobar (pcie_bdf_t bdf, unsigned int bar_index, struct pcie_bar *iobar)
	Get the I/O BAR at a specific BAR index.

bool	pcie_probe_iobar (pcie_bdf_t bdf, unsigned int index, struct pcie_bar *iobar)
	Probe the nth I/O BAR address assigned to an endpoint.

void	pcie_set_cmd (pcie_bdf_t bdf, uint32_t bits, bool on)
	Set or reset bits in the endpoint command/status register.

unsigned int	pcie_alloc_irq (pcie_bdf_t bdf)
	Allocate an IRQ for an endpoint.

unsigned int	pcie_get_irq (pcie_bdf_t bdf)
	Return the IRQ assigned by the firmware/board to an endpoint.

void	pcie_irq_enable (pcie_bdf_t bdf, unsigned int irq)
	Enable the PCI(e) endpoint to generate the specified IRQ.

uint32_t	pcie_get_cap (pcie_bdf_t bdf, uint32_t cap_id)
	Find a PCI(e) capability in an endpoint's configuration space.

uint32_t	pcie_get_ext_cap (pcie_bdf_t bdf, uint32_t cap_id)
	Find an Extended PCI(e) capability in an endpoint's configuration space.

bool	pcie_connect_dynamic_irq (pcie_bdf_t bdf, unsigned int irq, unsigned int priority, void(routine)(const void parameter), const void *parameter, uint32_t flags)
	Dynamically connect a PCIe endpoint IRQ to an ISR handler.

Detailed Description

PCIe Host Interface.

Macro Definition Documentation

◆ DEVICE_PCIE_DECLARE

#define DEVICE_PCIE_DECLARE ( node_id )

#include <zephyr/drivers/pcie/pcie.h>

Value:

        STRUCT_SECTION_ITERABLE(pcie_dev, Z_DEVICE_PCIE_NAME(node_id)) = {  \
                .bdf = PCIE_BDF_NONE,                                       \
                .id = PCIE_DT_ID(node_id),                                  \
                .class_rev = DT_PROP_OR(node_id, class_rev, 0),             \
                .class_rev_mask = DT_PROP_OR(node_id, class_rev_mask, 0),   \
        }

Declare a PCIe context variable for a DTS node.

Declares a PCIe context for a DTS node. This must be done before using the DEVICE_PCIE_INIT() macro for the same node.

Parameters

node_id DTS node identifier

◆ DEVICE_PCIE_INIT

#define DEVICE_PCIE_INIT	(	node_id,
		name
	)	.name = &Z_DEVICE_PCIE_NAME(node_id)

#include <zephyr/drivers/pcie/pcie.h>

Initialize a named struct member to point at a PCIe context.

Initialize PCIe-related information within a specific instance of a device config struct, using information from DTS. Using the macro requires having first created PCIe context struct using the DEVICE_PCIE_DECLARE() macro.

Example for an instance of a driver belonging to the "foo" subsystem

struct foo_config { struct pcie_dev *pcie; ... };

DEVICE_PCIE_ID_DECLARE(DT_DRV_INST(...)); struct foo_config my_config = { DEVICE_PCIE_INIT(pcie, DT_DRV_INST(...)), ... };

Parameters

node_id	DTS node identifier
name	Member name within config for the MMIO region

◆ DEVICE_PCIE_INST_DECLARE

#define DEVICE_PCIE_INST_DECLARE ( inst ) DEVICE_PCIE_DECLARE(DT_DRV_INST(inst))

#include <zephyr/drivers/pcie/pcie.h>

Declare a PCIe context variable for a DTS node.

This is equivalent to DEVICE_PCIE_DECLARE(DT_DRV_INST(inst))

Parameters

inst	Devicetree instance number

◆ DEVICE_PCIE_INST_INIT

#define DEVICE_PCIE_INST_INIT	(	inst,
		name
	)	DEVICE_PCIE_INIT(DT_DRV_INST(inst), name)

#include <zephyr/drivers/pcie/pcie.h>

Initialize a named struct member to point at a PCIe context.

This is equivalent to DEVICE_PCIE_INIT(DT_DRV_INST(inst), name)

Parameters

inst	Devicetree instance number
name	Name of the struct member (of type struct pcie_dev *)

◆ PCIE_BUS_NUMBER

#define PCIE_BUS_NUMBER 6U

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_BUS_NUMBER_VAL

#define PCIE_BUS_NUMBER_VAL	(	prim,
		sec,
		sub,
		lat
	)

#include <zephyr/drivers/pcie/pcie.h>

Value:

        (((prim) & 0xffUL) |                     \
         (((sec) & 0xffUL) << 8) |               \
         (((sub) & 0xffUL) << 16) |              \
         (((lat) & 0xffUL) << 24))

◆ PCIE_BUS_PRIMARY_NUMBER

#define PCIE_BUS_PRIMARY_NUMBER ( w ) ((w) & 0xffUL)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_BUS_SECONDARY_NUMBER

#define PCIE_BUS_SECONDARY_NUMBER ( w ) (((w) >> 8) & 0xffUL)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_BUS_SUBORDINATE_NUMBER

#define PCIE_BUS_SUBORDINATE_NUMBER ( w ) (((w) >> 16) & 0xffUL)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_BAR0

#define PCIE_CONF_BAR0 4U

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_BAR1

#define PCIE_CONF_BAR1 5U

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_BAR2

#define PCIE_CONF_BAR2 6U

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_BAR3

#define PCIE_CONF_BAR3 7U

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_BAR4

#define PCIE_CONF_BAR4 8U

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_BAR5

#define PCIE_CONF_BAR5 9U

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_BAR_64

#define PCIE_CONF_BAR_64 ( w ) (((w) & 0x00000006U) == 0x00000004U)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_BAR_ADDR

#define PCIE_CONF_BAR_ADDR ( w ) ((w) & ~0xfUL)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_BAR_FLAGS

#define PCIE_CONF_BAR_FLAGS ( w ) ((w) & 0xfUL)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_BAR_INVAL

#define PCIE_CONF_BAR_INVAL 0xFFFFFFF0U

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_BAR_INVAL64

#define PCIE_CONF_BAR_INVAL64 0xFFFFFFFFFFFFFFF0UL

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_BAR_INVAL_FLAGS

#define PCIE_CONF_BAR_INVAL_FLAGS ( w )

#include <zephyr/drivers/pcie/pcie.h>

Value:

((((w) & 0x00000006U) == 0x00000006U) || \

(((w) & 0x00000006U) == 0x00000002U))

◆ PCIE_CONF_BAR_IO

#define PCIE_CONF_BAR_IO ( w ) (((w) & 0x00000001U) == 0x00000001U)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_BAR_IO_ADDR

#define PCIE_CONF_BAR_IO_ADDR ( w ) ((w) & ~0x3UL)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_BAR_MEM

#define PCIE_CONF_BAR_MEM ( w ) (((w) & 0x00000001U) != 0x00000001U)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_BAR_NONE

#define PCIE_CONF_BAR_NONE 0U

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_CAP_ID

#define PCIE_CONF_CAP_ID ( w ) ((w) & 0xFFU)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_CAP_NEXT

#define PCIE_CONF_CAP_NEXT ( w ) (((w) >> 10) & 0x3FU)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_CAPPTR

#define PCIE_CONF_CAPPTR 13U /* capabilities pointer */

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_CAPPTR_FIRST

#define PCIE_CONF_CAPPTR_FIRST ( w ) (((w) >> 2) & 0x3FU)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_CLASSREV

#define PCIE_CONF_CLASSREV 2U /* class/revision register */

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_CLASSREV_CLASS

#define PCIE_CONF_CLASSREV_CLASS ( w ) (((w) >> 24) & 0xFFU)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_CLASSREV_PROGIF

#define PCIE_CONF_CLASSREV_PROGIF ( w ) (((w) >> 8) & 0xFFU)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_CLASSREV_REV

#define PCIE_CONF_CLASSREV_REV ( w ) ((w) & 0xFFU)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_CLASSREV_SUBCLASS

#define PCIE_CONF_CLASSREV_SUBCLASS ( w ) (((w) >> 16) & 0xFFU)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_CMDSTAT

#define PCIE_CONF_CMDSTAT 1U /* command/status register */

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_CMDSTAT_CAPS

#define PCIE_CONF_CMDSTAT_CAPS 0x00100000U /* capabilities list */

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_CMDSTAT_INTERRUPT

#define PCIE_CONF_CMDSTAT_INTERRUPT 0x00080000U /* interrupt status */

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_CMDSTAT_IO

#define PCIE_CONF_CMDSTAT_IO 0x00000001U /* I/O access enable */

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_CMDSTAT_MASTER

#define PCIE_CONF_CMDSTAT_MASTER 0x00000004U /* bus master enable */

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_CMDSTAT_MEM

#define PCIE_CONF_CMDSTAT_MEM 0x00000002U /* mem access enable */

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_EXT_CAP_ID

#define PCIE_CONF_EXT_CAP_ID ( w ) ((w) & 0xFFFFU)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_EXT_CAP_NEXT

#define PCIE_CONF_EXT_CAP_NEXT ( w ) (((w) >> 20) & 0xFFFU)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_EXT_CAP_VER

#define PCIE_CONF_EXT_CAP_VER ( w ) (((w) >> 16) & 0xFU)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_EXT_CAPPTR

#define PCIE_CONF_EXT_CAPPTR 64U

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_ID

#define PCIE_CONF_ID 0U

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_INTR

#define PCIE_CONF_INTR 15U

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_INTR_IRQ

#define PCIE_CONF_INTR_IRQ ( w ) ((w) & 0xFFU)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_INTR_IRQ_NONE

#define PCIE_CONF_INTR_IRQ_NONE 0xFFU /* no interrupt routed */

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_MULTIFUNCTION

#define PCIE_CONF_MULTIFUNCTION ( w ) (((w) & 0x00800000U) != 0U)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_TYPE

#define PCIE_CONF_TYPE 3U

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_TYPE_BRIDGE

#define PCIE_CONF_TYPE_BRIDGE ( w ) (((w) & 0x007F0000U) != 0U)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_TYPE_CARDBUS_BRIDGE

#define PCIE_CONF_TYPE_CARDBUS_BRIDGE 0x2U

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_TYPE_GET

#define PCIE_CONF_TYPE_GET ( w ) (((w) >> 16) & 0x7F)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_TYPE_PCI_BRIDGE

#define PCIE_CONF_TYPE_PCI_BRIDGE 0x1U

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_CONF_TYPE_STANDARD

#define PCIE_CONF_TYPE_STANDARD 0x0U

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_DT_ID

#define PCIE_DT_ID ( node_id )

#include <zephyr/drivers/pcie/pcie.h>

Value:

PCIE_ID(DT_PROP_OR(node_id, vendor_id, 0xffff), \

DT_PROP_OR(node_id, device_id, 0xffff))

PCIE_ID

#define PCIE_ID(vend, dev)

Definition: pcie.h:35

Get the PCIe Vendor and Device ID for a node.

Parameters

node_id DTS node identifier

Returns: The VID/DID combination as pcie_id_t

◆ PCIE_DT_INST_ID

#define PCIE_DT_INST_ID ( inst ) PCIE_DT_ID(DT_DRV_INST(inst))

#include <zephyr/drivers/pcie/pcie.h>

Get the PCIe Vendor and Device ID for a node.

This is equivalent to PCIE_DT_ID(DT_DRV_INST(inst))

Parameters

inst	Devicetree instance number

Returns: The VID/DID combination as pcie_id_t

◆ PCIE_HOST_CONTROLLER

#define PCIE_HOST_CONTROLLER ( n ) PCIE_BDF(0, 0, n)

#include <zephyr/drivers/pcie/pcie.h>

Get the BDF for a given PCI host controller.

This macro is useful when the PCI host controller behind PCIE_BDF(0, 0, 0) indicates a multifunction device. In such a case each function of this endpoint is a potential host controller itself.

Parameters

n	Bus number

Returns: BDF value of the given host controller

◆ PCIE_ID_IS_VALID

#define PCIE_ID_IS_VALID ( id )

#include <zephyr/drivers/pcie/pcie.h>

Value:

                              ((id != PCIE_ID_NONE) && \
                              (id != PCIE_ID(0x0000, 0x0000)) && \
                              (id != PCIE_ID(0xFFFF, 0x0000)) && \
                              (id != PCIE_ID(0x0000, 0xFFFF)))

◆ PCIE_IO_BASE

#define PCIE_IO_BASE ( w ) ((w) & 0xffUL)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_IO_BASE_LIMIT_UPPER

#define PCIE_IO_BASE_LIMIT_UPPER 12U

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_IO_BASE_LIMIT_UPPER_VAL

#define PCIE_IO_BASE_LIMIT_UPPER_VAL	(	iobu,
		iolu
	)

#include <zephyr/drivers/pcie/pcie.h>

Value:

(((iobu) & 0xffffUL) | \

(((iolu) & 0xffffUL) << 16))

◆ PCIE_IO_BASE_UPPER

#define PCIE_IO_BASE_UPPER ( w ) ((w) & 0xffffUL)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_IO_LIMIT

#define PCIE_IO_LIMIT ( w ) (((w) >> 8) & 0xffUL)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_IO_LIMIT_UPPER

#define PCIE_IO_LIMIT_UPPER ( w ) (((w) >> 16) & 0xffffUL)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_IO_SEC_STATUS

#define PCIE_IO_SEC_STATUS 7U

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_IO_SEC_STATUS_VAL

#define PCIE_IO_SEC_STATUS_VAL	(	iob,
		iol,
		sec_status
	)

#include <zephyr/drivers/pcie/pcie.h>

Value:

        (((iob) & 0xffUL) |                          \
         (((iol) & 0xffUL) << 8) |                   \
         (((sec_status) & 0xffffUL) << 16))

◆ PCIE_IRQ_CONNECT

#define PCIE_IRQ_CONNECT	(	bdf_p,
		irq_p,
		priority_p,
		isr_p,
		isr_param_p,
		flags_p
	)

#include <zephyr/drivers/pcie/pcie.h>

Value:

ARCH_PCIE_IRQ_CONNECT(bdf_p, irq_p, priority_p, \

isr_p, isr_param_p, flags_p)

Initialize an interrupt handler for a PCIe endpoint IRQ.

This routine is only meant to be used by drivers using PCIe bus and having fixed or MSI based IRQ (so no runtime detection of the IRQ). In case of runtime detection see pcie_connect_dynamic_irq()

Parameters

bdf_p	PCIe endpoint BDF
irq_p	IRQ line number.
priority_p	Interrupt priority.
isr_p	Address of interrupt service routine.
isr_param_p	Parameter passed to interrupt service routine.
flags_p	Architecture-specific IRQ configuration flags..

◆ PCIE_MAX_BUS

#define PCIE_MAX_BUS (0xFFFFFFFFU & PCIE_BDF_BUS_MASK)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_MAX_DEV

#define PCIE_MAX_DEV (0xFFFFFFFFU & PCIE_BDF_DEV_MASK)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_MAX_FUNC

#define PCIE_MAX_FUNC (0xFFFFFFFFU & PCIE_BDF_FUNC_MASK)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_MEM_BASE

#define PCIE_MEM_BASE ( w ) ((w) & 0xffffUL)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_MEM_BASE_LIMIT

#define PCIE_MEM_BASE_LIMIT 8U

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_MEM_BASE_LIMIT_VAL

#define PCIE_MEM_BASE_LIMIT_VAL	(	memb,
		meml
	)

#include <zephyr/drivers/pcie/pcie.h>

Value:

(((memb) & 0xffffUL) | \

(((meml) & 0xffffUL) << 16))

◆ PCIE_MEM_LIMIT

#define PCIE_MEM_LIMIT ( w ) (((w) >> 16) & 0xffffUL)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_PREFETCH_BASE

#define PCIE_PREFETCH_BASE ( w ) ((w) & 0xffffUL)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_PREFETCH_BASE_LIMIT

#define PCIE_PREFETCH_BASE_LIMIT 9U

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_PREFETCH_BASE_LIMIT_VAL

#define PCIE_PREFETCH_BASE_LIMIT_VAL	(	pmemb,
		pmeml
	)

#include <zephyr/drivers/pcie/pcie.h>

Value:

(((pmemb) & 0xffffUL) | \

(((pmeml) & 0xffffUL) << 16))

◆ PCIE_PREFETCH_BASE_UPPER

#define PCIE_PREFETCH_BASE_UPPER 10U

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_PREFETCH_LIMIT

#define PCIE_PREFETCH_LIMIT ( w ) (((w) >> 16) & 0xffffUL)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_PREFETCH_LIMIT_UPPER

#define PCIE_PREFETCH_LIMIT_UPPER 11U

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_SEC_STATUS

#define PCIE_SEC_STATUS ( w ) (((w) >> 16) & 0xffffUL)

#include <zephyr/drivers/pcie/pcie.h>

◆ PCIE_SECONDARY_LATENCY_TIMER

#define PCIE_SECONDARY_LATENCY_TIMER ( w ) (((w) >> 24) & 0xffUL)

#include <zephyr/drivers/pcie/pcie.h>

Typedef Documentation

◆ pcie_bdf_t

pcie_bdf_t

#include <zephyr/drivers/pcie/pcie.h>

A unique PCI(e) endpoint (bus, device, function).

A PCI(e) endpoint is uniquely identified topologically using a (bus, device, function) tuple. The internal structure is documented in include/dt-bindings/pcie/pcie.h: see PCIE_BDF() and friends, since these tuples are referenced from devicetree.

◆ pcie_id_t

pcie_id_t

#include <zephyr/drivers/pcie/pcie.h>

A unique PCI(e) identifier (vendor ID, device ID).

The PCIE_CONF_ID register for each endpoint is a (vendor ID, device ID) pair, which is meant to tell the system what the PCI(e) endpoint is. Again, look to PCIE_ID_* macros in include/dt-bindings/pcie/pcie.h for more.

◆ pcie_scan_cb_t

typedef bool(* pcie_scan_cb_t) (pcie_bdf_t bdf, pcie_id_t id, void *cb_data)

#include <zephyr/drivers/pcie/pcie.h>

Callback type used for scanning for PCI endpoints.

Parameters

bdf	BDF value for a found endpoint.
id	Vendor & Device ID for the found endpoint.
cb_data	Custom, use case specific data.

Returns: true to continue scanning, false to stop scanning.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum

#include <zephyr/drivers/pcie/pcie.h>

Enumerator
PCIE_SCAN_RECURSIVE	Scan all available PCI host controllers and sub-busses.
PCIE_SCAN_CB_ALL	Do the callback for all endpoint types, including bridges.

Function Documentation

◆ pcie_alloc_irq()

unsigned int pcie_alloc_irq ( pcie_bdf_t bdf )

#include <zephyr/drivers/pcie/pcie.h>

Allocate an IRQ for an endpoint.

This function first checks the IRQ register and if it contains a valid value this is returned. If the register does not contain a valid value allocation of a new one is attempted. Such function is only exposed if CONFIG_PCIE_CONTROLLER is unset. It is thus available where architecture tied dynamic IRQ allocation for PCIe device makes sense.

Parameters

bdf	the PCI(e) endpoint

Returns: the IRQ number, or PCIE_CONF_INTR_IRQ_NONE if allocation failed.

◆ pcie_conf_read()

uint32_t pcie_conf_read	(	pcie_bdf_t	bdf,
		unsigned int	reg
	)

#include <zephyr/drivers/pcie/pcie.h>

Read a 32-bit word from an endpoint's configuration space.

This function is exported by the arch/SoC/board code.

Parameters

bdf	PCI(e) endpoint
reg	the configuration word index (not address)

Returns: the word read (0xFFFFFFFFU if nonexistent endpoint or word)

◆ pcie_conf_write()

void pcie_conf_write	(	pcie_bdf_t	bdf,
		unsigned int	reg,
		uint32_t	data
	)

#include <zephyr/drivers/pcie/pcie.h>

Write a 32-bit word to an endpoint's configuration space.

This function is exported by the arch/SoC/board code.

Parameters

bdf	PCI(e) endpoint
reg	the configuration word index (not address)
data	the value to write

◆ pcie_connect_dynamic_irq()

bool pcie_connect_dynamic_irq	(	pcie_bdf_t	bdf,
		unsigned int	irq,
		unsigned int	priority,
		void()(const void parameter)	routine,
		const void *	parameter,
		uint32_t	flags
	)

#include <zephyr/drivers/pcie/pcie.h>

Dynamically connect a PCIe endpoint IRQ to an ISR handler.

Parameters

bdf	the PCI endpoint to examine
irq	the IRQ to connect (see pcie_alloc_irq())
priority	priority of the IRQ
routine	the ISR handler to connect to the IRQ
parameter	the parameter to provide to the handler
flags	IRQ connection flags

Returns: true if connected, false otherwise

◆ pcie_get_cap()

uint32_t pcie_get_cap	(	pcie_bdf_t	bdf,
		uint32_t	cap_id
	)

#include <zephyr/drivers/pcie/pcie.h>

Find a PCI(e) capability in an endpoint's configuration space.

Parameters

bdf	the PCI endpoint to examine
cap_id	the capability ID of interest

Returns: the index of the configuration word, or 0 if no capability.

◆ pcie_get_ext_cap()

uint32_t pcie_get_ext_cap	(	pcie_bdf_t	bdf,
		uint32_t	cap_id
	)

#include <zephyr/drivers/pcie/pcie.h>

Find an Extended PCI(e) capability in an endpoint's configuration space.

Parameters

bdf	the PCI endpoint to examine
cap_id	the capability ID of interest

Returns: the index of the configuration word, or 0 if no capability.

◆ pcie_get_iobar()

bool pcie_get_iobar	(	pcie_bdf_t	bdf,
		unsigned int	bar_index,
		struct pcie_bar *	iobar
	)

#include <zephyr/drivers/pcie/pcie.h>

Get the I/O BAR at a specific BAR index.

Parameters

bdf	the PCI(e) endpoint
bar_index	0-based BAR index
iobar	Pointer to struct pcie_bar

Returns: true if the I/O BAR was found and is valid, false otherwise

◆ pcie_get_irq()

unsigned int pcie_get_irq ( pcie_bdf_t bdf )

#include <zephyr/drivers/pcie/pcie.h>

Return the IRQ assigned by the firmware/board to an endpoint.

Parameters

bdf	the PCI(e) endpoint

Returns: the IRQ number, or PCIE_CONF_INTR_IRQ_NONE if unknown.

◆ pcie_get_mbar()

bool pcie_get_mbar	(	pcie_bdf_t	bdf,
		unsigned int	bar_index,
		struct pcie_bar *	mbar
	)

#include <zephyr/drivers/pcie/pcie.h>

Get the MBAR at a specific BAR index.

Parameters

bdf	the PCI(e) endpoint
bar_index	0-based BAR index
mbar	Pointer to struct pcie_bar

Returns: true if the mbar was found and is valid, false otherwise

◆ pcie_irq_enable()

void pcie_irq_enable	(	pcie_bdf_t	bdf,
		unsigned int	irq
	)

#include <zephyr/drivers/pcie/pcie.h>

Enable the PCI(e) endpoint to generate the specified IRQ.

Parameters

bdf	the PCI(e) endpoint
irq	the IRQ to generate

If MSI is enabled and the endpoint supports it, the endpoint will be configured to generate the specified IRQ via MSI. Otherwise, it is assumed that the IRQ has been routed by the boot firmware to the specified IRQ, and the IRQ is enabled (at the I/O APIC, or wherever appropriate).

◆ pcie_probe_iobar()

bool pcie_probe_iobar	(	pcie_bdf_t	bdf,
		unsigned int	index,
		struct pcie_bar *	iobar
	)

#include <zephyr/drivers/pcie/pcie.h>

Probe the nth I/O BAR address assigned to an endpoint.

Parameters

bdf	the PCI(e) endpoint
index	(0-based) index
iobar	Pointer to struct pcie_bar

Returns: true if the I/O BAR was found and is valid, false otherwise

A PCI(e) endpoint has 0 or more I/O regions. This function allows the caller to enumerate them by calling with index=0..n. Value of n has to be below 6, as there is a maximum of 6 BARs. The indices are order-preserving with respect to the endpoint BARs: e.g., index 0 will return the lowest-numbered I/O BAR on the endpoint.

◆ pcie_probe_mbar()

bool pcie_probe_mbar	(	pcie_bdf_t	bdf,
		unsigned int	index,
		struct pcie_bar *	mbar
	)

#include <zephyr/drivers/pcie/pcie.h>

Probe the nth MMIO address assigned to an endpoint.

Parameters

bdf	the PCI(e) endpoint
index	(0-based) index
mbar	Pointer to struct pcie_bar

Returns: true if the mbar was found and is valid, false otherwise

A PCI(e) endpoint has 0 or more memory-mapped regions. This function allows the caller to enumerate them by calling with index=0..n. Value of n has to be below 6, as there is a maximum of 6 BARs. The indices are order-preserving with respect to the endpoint BARs: e.g., index 0 will return the lowest-numbered memory BAR on the endpoint.

◆ pcie_scan()

int pcie_scan ( const struct pcie_scan_opt * opt )

#include <zephyr/drivers/pcie/pcie.h>

Scan for PCIe devices.

Scan the PCI bus (or busses) for available endpoints.

Parameters

opt	Options determining how to perform the scan.

Returns: 0 on success, negative POSIX error number on failure.

◆ pcie_set_cmd()

void pcie_set_cmd	(	pcie_bdf_t	bdf,
		uint32_t	bits,
		bool	on
	)

#include <zephyr/drivers/pcie/pcie.h>

Set or reset bits in the endpoint command/status register.

Parameters

bdf	the PCI(e) endpoint
bits	the powerset of bits of interest
on	use true to set bits, false to reset them

Modules

Data Structures

Macros

Typedefs

Enumerations

Functions

Detailed Description

Macro Definition Documentation

◆ DEVICE_PCIE_DECLARE

◆ DEVICE_PCIE_INIT

◆ DEVICE_PCIE_INST_DECLARE

◆ DEVICE_PCIE_INST_INIT

◆ PCIE_BUS_NUMBER

◆ PCIE_BUS_NUMBER_VAL

◆ PCIE_BUS_PRIMARY_NUMBER

◆ PCIE_BUS_SECONDARY_NUMBER

◆ PCIE_BUS_SUBORDINATE_NUMBER

◆ PCIE_CONF_BAR0

◆ PCIE_CONF_BAR1

◆ PCIE_CONF_BAR2

◆ PCIE_CONF_BAR3

◆ PCIE_CONF_BAR4

◆ PCIE_CONF_BAR5

◆ PCIE_CONF_BAR_64

◆ PCIE_CONF_BAR_ADDR

◆ PCIE_CONF_BAR_FLAGS

◆ PCIE_CONF_BAR_INVAL

◆ PCIE_CONF_BAR_INVAL64

◆ PCIE_CONF_BAR_INVAL_FLAGS

◆ PCIE_CONF_BAR_IO

◆ PCIE_CONF_BAR_IO_ADDR

◆ PCIE_CONF_BAR_MEM

◆ PCIE_CONF_BAR_NONE

◆ PCIE_CONF_CAP_ID

◆ PCIE_CONF_CAP_NEXT

◆ PCIE_CONF_CAPPTR

◆ PCIE_CONF_CAPPTR_FIRST

◆ PCIE_CONF_CLASSREV

◆ PCIE_CONF_CLASSREV_CLASS

◆ PCIE_CONF_CLASSREV_PROGIF

◆ PCIE_CONF_CLASSREV_REV

◆ PCIE_CONF_CLASSREV_SUBCLASS

◆ PCIE_CONF_CMDSTAT

◆ PCIE_CONF_CMDSTAT_CAPS

◆ PCIE_CONF_CMDSTAT_INTERRUPT

◆ PCIE_CONF_CMDSTAT_IO

◆ PCIE_CONF_CMDSTAT_MASTER

◆ PCIE_CONF_CMDSTAT_MEM

◆ PCIE_CONF_EXT_CAP_ID

◆ PCIE_CONF_EXT_CAP_NEXT

◆ PCIE_CONF_EXT_CAP_VER

◆ PCIE_CONF_EXT_CAPPTR

◆ PCIE_CONF_ID

◆ PCIE_CONF_INTR

◆ PCIE_CONF_INTR_IRQ

◆ PCIE_CONF_INTR_IRQ_NONE

◆ PCIE_CONF_MULTIFUNCTION

◆ PCIE_CONF_TYPE

◆ PCIE_CONF_TYPE_BRIDGE

◆ PCIE_CONF_TYPE_CARDBUS_BRIDGE

◆ PCIE_CONF_TYPE_GET

◆ PCIE_CONF_TYPE_PCI_BRIDGE

◆ PCIE_CONF_TYPE_STANDARD

◆ PCIE_DT_ID

◆ PCIE_DT_INST_ID

◆ PCIE_HOST_CONTROLLER

◆ PCIE_ID_IS_VALID

◆ PCIE_IO_BASE

◆ PCIE_IO_BASE_LIMIT_UPPER

◆ PCIE_IO_BASE_LIMIT_UPPER_VAL

◆ PCIE_IO_BASE_UPPER

◆ PCIE_IO_LIMIT

◆ PCIE_IO_LIMIT_UPPER

◆ PCIE_IO_SEC_STATUS

◆ PCIE_IO_SEC_STATUS_VAL

◆ PCIE_IRQ_CONNECT

◆ PCIE_MAX_BUS

◆ PCIE_MAX_DEV

◆ PCIE_MAX_FUNC

◆ PCIE_MEM_BASE