Cache Controller Interface

Cache Controller Interface. More...

Macros
#define	cache_data_enable   arch_dcache_enable
#define	cache_data_disable   arch_dcache_disable
#define	cache_data_flush_all   arch_dcache_flush_all
#define	cache_data_invd_all   arch_dcache_invd_all
#define	cache_data_flush_and_invd_all   arch_dcache_flush_and_invd_all
#define	cache_data_flush_range(addr, size)   arch_dcache_flush_range(addr, size)
#define	cache_data_invd_range(addr, size)   arch_dcache_invd_range(addr, size)
#define	cache_data_flush_and_invd_range(addr, size)    arch_dcache_flush_and_invd_range(addr, size)
#define	cache_data_line_size_get   arch_dcache_line_size_get
#define	cache_instr_enable   arch_icache_enable
#define	cache_instr_disable   arch_icache_disable
#define	cache_instr_flush_all   arch_icache_flush_all
#define	cache_instr_invd_all   arch_icache_invd_all
#define	cache_instr_flush_and_invd_all   arch_icache_flush_and_invd_all
#define	cache_instr_flush_range(addr, size)   arch_icache_flush_range(addr, size)
#define	cache_instr_invd_range(addr, size)   arch_icache_invd_range(addr, size)
#define	cache_instr_flush_and_invd_range(addr, size)    arch_icache_flush_and_invd_range(addr, size)
#define	cache_instr_line_size_get   arch_icache_line_size_get
#define	cache_is_ptr_cached(ptr)   arch_cache_is_ptr_cached(ptr)
#define	cache_is_ptr_uncached(ptr)   arch_cache_is_ptr_uncached(ptr)
#define	cache_cached_ptr(ptr)   arch_cache_cached_ptr_get(ptr)
#define	cache_uncached_ptr(ptr)   arch_cache_uncached_ptr_get(ptr)

Functions
void	arch_dcache_enable (void)
	Enable the d-cache.
void	arch_dcache_disable (void)
	Disable the d-cache.
int	arch_dcache_flush_all (void)
	Flush the d-cache.
int	arch_dcache_invd_all (void)
	Invalidate the d-cache.
int	arch_dcache_flush_and_invd_all (void)
	Flush and Invalidate the d-cache.
int	arch_dcache_flush_range (void *addr, size_t size)
	Flush an address range in the d-cache.
int	arch_dcache_invd_range (void *addr, size_t size)
	Invalidate an address range in the d-cache.
int	arch_dcache_flush_and_invd_range (void *addr, size_t size)
	Flush and Invalidate an address range in the d-cache.
size_t	arch_dcache_line_size_get (void)
	Get the d-cache line size.
void	arch_icache_enable (void)
	Enable the i-cache.
void	arch_icache_disable (void)
	Disable the i-cache.
int	arch_icache_flush_all (void)
	Flush the i-cache.
int	arch_icache_invd_all (void)
	Invalidate the i-cache.
int	arch_icache_flush_and_invd_all (void)
	Flush and Invalidate the i-cache.
int	arch_icache_flush_range (void *addr, size_t size)
	Flush an address range in the i-cache.
int	arch_icache_invd_range (void *addr, size_t size)
	Invalidate an address range in the i-cache.
int	arch_icache_flush_and_invd_range (void *addr, size_t size)
	Flush and Invalidate an address range in the i-cache.
size_t	arch_icache_line_size_get (void)
	Get the i-cache line size.
bool	arch_cache_is_ptr_cached (void *ptr)
bool	arch_cache_is_ptr_uncached (void *ptr)
void *	arch_cache_cached_ptr_get (void *ptr)
void *	arch_cache_uncached_ptr_get (void *ptr)

Detailed Description

Cache Controller Interface.

Macro Definition Documentation

cache_cached_ptr

#define cache_cached_ptr

(

ptr

)

arch_cache_cached_ptr_get(ptr)

#include <zephyr/arch/cache.h>

cache_data_disable

#define cache_data_disable   arch_dcache_disable

#include <zephyr/arch/cache.h>

cache_data_enable

#define cache_data_enable   arch_dcache_enable

#include <zephyr/arch/cache.h>

cache_data_flush_all

#define cache_data_flush_all   arch_dcache_flush_all

#include <zephyr/arch/cache.h>

cache_data_flush_and_invd_all

#define cache_data_flush_and_invd_all   arch_dcache_flush_and_invd_all

#include <zephyr/arch/cache.h>

cache_data_flush_and_invd_range

#define cache_data_flush_and_invd_range	(		addr,
			size
	)		arch_dcache_flush_and_invd_range(addr, size)

#include <zephyr/arch/cache.h>

cache_data_flush_range

#define cache_data_flush_range	(		addr,
			size
	)		arch_dcache_flush_range(addr, size)

#include <zephyr/arch/cache.h>

cache_data_invd_all

#define cache_data_invd_all   arch_dcache_invd_all

#include <zephyr/arch/cache.h>

cache_data_invd_range

#define cache_data_invd_range	(		addr,
			size
	)		arch_dcache_invd_range(addr, size)

#include <zephyr/arch/cache.h>

cache_data_line_size_get

#define cache_data_line_size_get   arch_dcache_line_size_get

#include <zephyr/arch/cache.h>

cache_instr_disable

#define cache_instr_disable   arch_icache_disable

#include <zephyr/arch/cache.h>

cache_instr_enable

#define cache_instr_enable   arch_icache_enable

#include <zephyr/arch/cache.h>

cache_instr_flush_all

#define cache_instr_flush_all   arch_icache_flush_all

#include <zephyr/arch/cache.h>

cache_instr_flush_and_invd_all

#define cache_instr_flush_and_invd_all   arch_icache_flush_and_invd_all

#include <zephyr/arch/cache.h>

cache_instr_flush_and_invd_range

#define cache_instr_flush_and_invd_range	(		addr,
			size
	)		arch_icache_flush_and_invd_range(addr, size)

#include <zephyr/arch/cache.h>

cache_instr_flush_range

#define cache_instr_flush_range	(		addr,
			size
	)		arch_icache_flush_range(addr, size)

#include <zephyr/arch/cache.h>

cache_instr_invd_all

#define cache_instr_invd_all   arch_icache_invd_all

#include <zephyr/arch/cache.h>

cache_instr_invd_range

#define cache_instr_invd_range	(		addr,
			size
	)		arch_icache_invd_range(addr, size)

#include <zephyr/arch/cache.h>

cache_instr_line_size_get

#define cache_instr_line_size_get   arch_icache_line_size_get

#include <zephyr/arch/cache.h>

cache_is_ptr_cached

#define cache_is_ptr_cached

(

ptr

)

arch_cache_is_ptr_cached(ptr)

#include <zephyr/arch/cache.h>

cache_is_ptr_uncached

#define cache_is_ptr_uncached

(

ptr

)

arch_cache_is_ptr_uncached(ptr)

#include <zephyr/arch/cache.h>

cache_uncached_ptr

#define cache_uncached_ptr

(

ptr

)

arch_cache_uncached_ptr_get(ptr)

#include <zephyr/arch/cache.h>

Function Documentation

arch_cache_cached_ptr_get()

void * arch_cache_cached_ptr_get

(

void *

ptr

)

#include <zephyr/arch/cache.h>

arch_cache_is_ptr_cached()

bool arch_cache_is_ptr_cached

(

void *

ptr

)

#include <zephyr/arch/cache.h>

arch_cache_is_ptr_uncached()

bool arch_cache_is_ptr_uncached

(

void *

ptr

)

#include <zephyr/arch/cache.h>

arch_cache_uncached_ptr_get()

void * arch_cache_uncached_ptr_get

(

void *

ptr

)

#include <zephyr/arch/cache.h>

arch_dcache_disable()

void arch_dcache_disable

(

void

)

#include <zephyr/arch/cache.h>

Disable the d-cache.

Disable the data cache.

arch_dcache_enable()

void arch_dcache_enable

(

void

)

#include <zephyr/arch/cache.h>

Enable the d-cache.

Enable the data cache.

arch_dcache_flush_all()

int arch_dcache_flush_all

(

void

)

#include <zephyr/arch/cache.h>

Flush the d-cache.

Flush the whole data cache.

Return values

0	If succeeded.
-ENOTSUP	If not supported.
-errno	Negative errno for other failures.

arch_dcache_flush_and_invd_all()

int arch_dcache_flush_and_invd_all

(

void

)

#include <zephyr/arch/cache.h>

Flush and Invalidate the d-cache.

Flush and Invalidate the whole data cache.

Return values

0	If succeeded.
-ENOTSUP	If not supported.
-errno	Negative errno for other failures.

arch_dcache_flush_and_invd_range()

int arch_dcache_flush_and_invd_range	(	void *	addr,
		size_t	size
	)

#include <zephyr/arch/cache.h>

Flush and Invalidate an address range in the d-cache.

Flush and Invalidate the specified address range of the data cache.

Note

the cache operations act on cache line. When multiple data structures share the same cache line being flushed, all the portions of the data structures sharing the same line will be flushed before being invalidated. This is usually not a problem because writing back is a non-destructive process that could be triggered by hardware at any time, so having an aligned addr or a padded size is not strictly necessary.

Parameters

addr	Starting address to flush and invalidate.
size	Range size.

Return values

0	If succeeded.
-ENOTSUP	If not supported.
-errno	Negative errno for other failures.

arch_dcache_flush_range()

int arch_dcache_flush_range	(	void *	addr,
		size_t	size
	)

#include <zephyr/arch/cache.h>

Flush an address range in the d-cache.

Flush the specified address range of the data cache.

Note

the cache operations act on cache line. When multiple data structures share the same cache line being flushed, all the portions of the data structures sharing the same line will be flushed. This is usually not a problem because writing back is a non-destructive process that could be triggered by hardware at any time, so having an aligned addr or a padded size is not strictly necessary.

Parameters

addr	Starting address to flush.
size	Range size.

Return values

0	If succeeded.
-ENOTSUP	If not supported.
-errno	Negative errno for other failures.

arch_dcache_invd_all()

int arch_dcache_invd_all

(

void

)

#include <zephyr/arch/cache.h>

Invalidate the d-cache.

Invalidate the whole data cache.

Return values

0	If succeeded.
-ENOTSUP	If not supported.
-errno	Negative errno for other failures.

arch_dcache_invd_range()

int arch_dcache_invd_range	(	void *	addr,
		size_t	size
	)

#include <zephyr/arch/cache.h>

Invalidate an address range in the d-cache.

Invalidate the specified address range of the data cache.

Note

the cache operations act on cache line. When multiple data structures share the same cache line being invalidated, all the portions of the non-read-only data structures sharing the same line will be invalidated as well. This is a destructive process that could lead to data loss and/or corruption. When addr is not aligned to the cache line and/or size is not a multiple of the cache line size the behaviour is undefined.

Parameters

addr	Starting address to invalidate.
size	Range size.

Return values

0	If succeeded.
-ENOTSUP	If not supported.
-errno	Negative errno for other failures.

arch_dcache_line_size_get()

size_t arch_dcache_line_size_get

(

void

)

#include <zephyr/arch/cache.h>

Get the d-cache line size.

The API is provided to dynamically detect the data cache line size at run time.

The function must be implemented only when CONFIG_DCACHE_LINE_SIZE_DETECT is defined.

Return values

size	Size of the d-cache line.
0	If the d-cache is not enabled.

arch_icache_disable()

void arch_icache_disable

(

void

)

#include <zephyr/arch/cache.h>

Disable the i-cache.

Disable the instruction cache.

arch_icache_enable()

void arch_icache_enable

(

void

)

#include <zephyr/arch/cache.h>

Enable the i-cache.

Enable the instruction cache.

arch_icache_flush_all()

int arch_icache_flush_all

(

void

)

#include <zephyr/arch/cache.h>

Flush the i-cache.

Flush the whole instruction cache.

Return values

0	If succeeded.
-ENOTSUP	If not supported.
-errno	Negative errno for other failures.

arch_icache_flush_and_invd_all()

int arch_icache_flush_and_invd_all

(

void

)

#include <zephyr/arch/cache.h>

Flush and Invalidate the i-cache.

Flush and Invalidate the whole instruction cache.

Return values

0	If succeeded.
-ENOTSUP	If not supported.
-errno	Negative errno for other failures.

arch_icache_flush_and_invd_range()

int arch_icache_flush_and_invd_range	(	void *	addr,
		size_t	size
	)

#include <zephyr/arch/cache.h>

Flush and Invalidate an address range in the i-cache.

Flush and Invalidate the specified address range of the instruction cache.

Note

the cache operations act on cache line. When multiple data structures share the same cache line being flushed, all the portions of the data structures sharing the same line will be flushed before being invalidated. This is usually not a problem because writing back is a non-destructive process that could be triggered by hardware at any time, so having an aligned addr or a padded size is not strictly necessary.

Parameters

addr	Starting address to flush and invalidate.
size	Range size.

Return values

0	If succeeded.
-ENOTSUP	If not supported.
-errno	Negative errno for other failures.

arch_icache_flush_range()

int arch_icache_flush_range	(	void *	addr,
		size_t	size
	)

#include <zephyr/arch/cache.h>

Flush an address range in the i-cache.

Flush the specified address range of the instruction cache.

Note

the cache operations act on cache line. When multiple data structures share the same cache line being flushed, all the portions of the data structures sharing the same line will be flushed. This is usually not a problem because writing back is a non-destructive process that could be triggered by hardware at any time, so having an aligned addr or a padded size is not strictly necessary.

Parameters

addr	Starting address to flush.
size	Range size.

Return values

0	If succeeded.
-ENOTSUP	If not supported.
-errno	Negative errno for other failures.

arch_icache_invd_all()

int arch_icache_invd_all

(

void

)

#include <zephyr/arch/cache.h>

Invalidate the i-cache.

Invalidate the whole instruction cache.

Return values

0	If succeeded.
-ENOTSUP	If not supported.
-errno	Negative errno for other failures.

arch_icache_invd_range()

int arch_icache_invd_range	(	void *	addr,
		size_t	size
	)

#include <zephyr/arch/cache.h>

Invalidate an address range in the i-cache.

Invalidate the specified address range of the instruction cache.

Note

the cache operations act on cache line. When multiple data structures share the same cache line being invalidated, all the portions of the non-read-only data structures sharing the same line will be invalidated as well. This is a destructive process that could lead to data loss and/or corruption. When addr is not aligned to the cache line and/or size is not a multiple of the cache line size the behaviour is undefined.

Parameters

addr	Starting address to invalidate.
size	Range size.

Return values

0	If succeeded.
-ENOTSUP	If not supported.
-errno	Negative errno for other failures.

arch_icache_line_size_get()

size_t arch_icache_line_size_get

(

void

)

#include <zephyr/arch/cache.h>

Get the i-cache line size.

The API is provided to dynamically detect the instruction cache line size at run time.

The function must be implemented only when CONFIG_ICACHE_LINE_SIZE_DETECT is defined.

Return values

size	Size of the d-cache line.
0	If the d-cache is not enabled.