Zephyr API Documentation  3.6.99
A Scalable Open Source RTOS
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controller.h
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1
7/*
8 * Copyright (c) 2021 BayLibre, SAS
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 */
12#ifndef ZEPHYR_INCLUDE_DRIVERS_PCIE_CONTROLLERS_H_
13#define ZEPHYR_INCLUDE_DRIVERS_PCIE_CONTROLLERS_H_
14
15#include <zephyr/types.h>
16#include <zephyr/device.h>
17
18#ifdef CONFIG_PCIE_MSI
20#endif
21
29#ifdef __cplusplus
30extern "C" {
31#endif
32
44typedef uint32_t (*pcie_ctrl_conf_read_t)(const struct device *dev, pcie_bdf_t bdf,
45 unsigned int reg);
46
58typedef void (*pcie_ctrl_conf_write_t)(const struct device *dev, pcie_bdf_t bdf,
59 unsigned int reg, uint32_t data);
60
78typedef bool (*pcie_ctrl_region_allocate_t)(const struct device *dev, pcie_bdf_t bdf,
79 bool mem, bool mem64, size_t bar_size,
80 uintptr_t *bar_bus_addr);
81
98 bool mem, bool mem64, size_t align,
99 uintptr_t *bar_base_addr);
100
120typedef bool (*pcie_ctrl_region_translate_t)(const struct device *dev, pcie_bdf_t bdf,
121 bool mem, bool mem64, uintptr_t bar_bus_addr,
122 uintptr_t *bar_addr);
123
124#ifdef CONFIG_PCIE_MSI
125typedef uint8_t (*pcie_ctrl_msi_device_setup_t)(const struct device *dev, unsigned int priority,
126 msi_vector_t *vectors, uint8_t n_vector);
127#endif
128
142
143
157 unsigned int reg, uint32_t data);
158
169void pcie_generic_ctrl_enumerate(const struct device *dev, pcie_bdf_t bdf_start);
170
174__subsystem struct pcie_ctrl_driver_api {
180#ifdef CONFIG_PCIE_MSI
181 pcie_ctrl_msi_device_setup_t msi_device_setup;
182#endif
183};
184
196static inline uint32_t pcie_ctrl_conf_read(const struct device *dev, pcie_bdf_t bdf,
197 unsigned int reg)
198{
199 const struct pcie_ctrl_driver_api *api =
200 (const struct pcie_ctrl_driver_api *)dev->api;
201
202 return api->conf_read(dev, bdf, reg);
203}
204
216static inline void pcie_ctrl_conf_write(const struct device *dev, pcie_bdf_t bdf,
217 unsigned int reg, uint32_t data)
218{
219 const struct pcie_ctrl_driver_api *api =
220 (const struct pcie_ctrl_driver_api *)dev->api;
221
222 api->conf_write(dev, bdf, reg, data);
223}
224
242static inline bool pcie_ctrl_region_allocate(const struct device *dev, pcie_bdf_t bdf,
243 bool mem, bool mem64, size_t bar_size,
244 uintptr_t *bar_bus_addr)
245{
246 const struct pcie_ctrl_driver_api *api =
247 (const struct pcie_ctrl_driver_api *)dev->api;
248
249 return api->region_allocate(dev, bdf, mem, mem64, bar_size, bar_bus_addr);
250}
251
267static inline bool pcie_ctrl_region_get_allocate_base(const struct device *dev, pcie_bdf_t bdf,
268 bool mem, bool mem64, size_t align,
269 uintptr_t *bar_base_addr)
270{
271 const struct pcie_ctrl_driver_api *api =
272 (const struct pcie_ctrl_driver_api *)dev->api;
273
274 return api->region_get_allocate_base(dev, bdf, mem, mem64, align, bar_base_addr);
275}
276
295static inline bool pcie_ctrl_region_translate(const struct device *dev, pcie_bdf_t bdf,
296 bool mem, bool mem64, uintptr_t bar_bus_addr,
297 uintptr_t *bar_addr)
298{
299 const struct pcie_ctrl_driver_api *api =
300 (const struct pcie_ctrl_driver_api *)dev->api;
301
302 if (!api->region_translate) {
303 *bar_addr = bar_bus_addr;
304 return true;
305 } else {
306 return api->region_translate(dev, bdf, mem, mem64, bar_bus_addr, bar_addr);
307 }
308}
309
310#ifdef CONFIG_PCIE_MSI
311static inline uint8_t pcie_ctrl_msi_device_setup(const struct device *dev, unsigned int priority,
312 msi_vector_t *vectors, uint8_t n_vector)
313{
314 const struct pcie_ctrl_driver_api *api =
315 (const struct pcie_ctrl_driver_api *)dev->api;
316
317 return api->msi_device_setup(dev, priority, vectors, n_vector);
318}
319#endif
320
324#ifdef CONFIG_PCIE_MSI
325 const struct device *msi_parent;
326#endif
327 /* Configuration space physical address */
329 /* Configuration space physical size */
330 size_t cfg_size;
331 /* BAR regions translation ranges count */
333 /* BAR regions translation ranges table */
334 struct {
335 /* Flags as defined in the PCI Bus Binding to IEEE Std 1275-1994 */
337 /* bus-centric offset from the start of the region */
339 /* CPU-centric offset from the start of the region */
341 /* region size */
344};
345
346/*
347 * Fills the pcie_ctrl_config.ranges table from DT
348 */
349#define PCIE_RANGE_FORMAT(node_id, idx) \
350{ \
351 .flags = DT_RANGES_CHILD_BUS_FLAGS_BY_IDX(node_id, idx), \
352 .pcie_bus_addr = DT_RANGES_CHILD_BUS_ADDRESS_BY_IDX(node_id, idx), \
353 .host_map_addr = DT_RANGES_PARENT_BUS_ADDRESS_BY_IDX(node_id, idx), \
354 .map_length = DT_RANGES_LENGTH_BY_IDX(node_id, idx), \
355},
356
357#ifdef __cplusplus
358}
359#endif
360
365#endif /* ZEPHYR_INCLUDE_DRIVERS_PCIE_CONTROLLERS_H_ */
static uint32_t pcie_ctrl_conf_read(const struct device *dev, pcie_bdf_t bdf, unsigned int reg)
Read a 32-bit word from an endpoint's configuration space.
Definition: controller.h:196
static bool pcie_ctrl_region_allocate(const struct device *dev, pcie_bdf_t bdf, bool mem, bool mem64, size_t bar_size, uintptr_t *bar_bus_addr)
Allocate a memory region subset for an endpoint Base Address Register.
Definition: controller.h:242
void(* pcie_ctrl_conf_write_t)(const struct device *dev, pcie_bdf_t bdf, unsigned int reg, uint32_t data)
Function called to write a 32-bit word to an endpoint's configuration space.
Definition: controller.h:58
static void pcie_ctrl_conf_write(const struct device *dev, pcie_bdf_t bdf, unsigned int reg, uint32_t data)
Write a 32-bit word to an endpoint's configuration space.
Definition: controller.h:216
bool(* pcie_ctrl_region_allocate_t)(const struct device *dev, pcie_bdf_t bdf, bool mem, bool mem64, size_t bar_size, uintptr_t *bar_bus_addr)
Function called to allocate a memory region subset for an endpoint Base Address Register.
Definition: controller.h:78
void pcie_generic_ctrl_conf_write(mm_reg_t cfg_addr, pcie_bdf_t bdf, unsigned int reg, uint32_t data)
Write a 32-bit word to a Memory-Mapped endpoint's configuration space.
void pcie_generic_ctrl_enumerate(const struct device *dev, pcie_bdf_t bdf_start)
Start PCIe Endpoints enumeration.
uint32_t pcie_generic_ctrl_conf_read(mm_reg_t cfg_addr, pcie_bdf_t bdf, unsigned int reg)
Read a 32-bit word from a Memory-Mapped endpoint's configuration space.
bool(* pcie_ctrl_region_get_allocate_base_t)(const struct device *dev, pcie_bdf_t bdf, bool mem, bool mem64, size_t align, uintptr_t *bar_base_addr)
Function called to get the current allocation base of a memory region subset for an endpoint Base Add...
Definition: controller.h:97
bool(* pcie_ctrl_region_translate_t)(const struct device *dev, pcie_bdf_t bdf, bool mem, bool mem64, uintptr_t bar_bus_addr, uintptr_t *bar_addr)
Function called to translate an endpoint Base Address Register bus-centric address into Physical addr...
Definition: controller.h:120
uint32_t(* pcie_ctrl_conf_read_t)(const struct device *dev, pcie_bdf_t bdf, unsigned int reg)
Function called to read a 32-bit word from an endpoint's configuration space.
Definition: controller.h:44
static bool pcie_ctrl_region_translate(const struct device *dev, pcie_bdf_t bdf, bool mem, bool mem64, uintptr_t bar_bus_addr, uintptr_t *bar_addr)
Translate an endpoint Base Address Register bus-centric address into Physical address.
Definition: controller.h:295
static bool pcie_ctrl_region_get_allocate_base(const struct device *dev, pcie_bdf_t bdf, bool mem, bool mem64, size_t align, uintptr_t *bar_base_addr)
Function called to get the current allocation base of a memory region subset for an endpoint Base Add...
Definition: controller.h:267
uint32_t pcie_bdf_t
A unique PCI(e) endpoint (bus, device, function).
Definition: pcie.h:37
#define bool
Definition: stdbool.h:13
__UINT32_TYPE__ uint32_t
Definition: stdint.h:90
__UINT8_TYPE__ uint8_t
Definition: stdint.h:88
__UINTPTR_TYPE__ uintptr_t
Definition: stdint.h:105
Runtime device structure (in ROM) per driver instance.
Definition: device.h:399
void * data
Address of the device instance private data.
Definition: device.h:409
const void * api
Address of the API structure exposed by the device instance.
Definition: device.h:405
Definition: msi.h:51
Structure describing a device that supports the PCI Express Controller API.
Definition: controller.h:323
struct pcie_ctrl_config::@189 ranges[]
uintptr_t cfg_addr
Definition: controller.h:328
uintptr_t pcie_bus_addr
Definition: controller.h:338
size_t ranges_count
Definition: controller.h:332
uint32_t flags
Definition: controller.h:336
uintptr_t host_map_addr
Definition: controller.h:340
size_t cfg_size
Definition: controller.h:330
size_t map_length
Definition: controller.h:342
Structure providing callbacks to be implemented for devices that supports the PCI Express Controller ...
Definition: controller.h:174
pcie_ctrl_conf_read_t conf_read
Definition: controller.h:175
pcie_ctrl_region_allocate_t region_allocate
Definition: controller.h:177
pcie_ctrl_conf_write_t conf_write
Definition: controller.h:176
pcie_ctrl_region_get_allocate_base_t region_get_allocate_base
Definition: controller.h:178
pcie_ctrl_region_translate_t region_translate
Definition: controller.h:179
uintptr_t mm_reg_t
Definition: sys_io.h:20