#include <zephyr/arch/arm/exc.h>
Go to the source code of this file.
|
enum | AARCH32_GDB_REG {
R0 = 0
, R1
, R2
, R3
,
R4
, R5
, R6
, R7
,
R8
, R9
, R10
, R11
,
R12
, R13
, LR
, PC
,
SPSR
, GDB_NUM_REGS
} |
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◆ DBGDBCR_BRK_EN_MASK
#define DBGDBCR_BRK_EN_MASK 0x1 |
◆ DBGDBCR_BYTE_ADDR_MASK
#define DBGDBCR_BYTE_ADDR_MASK 0xF |
◆ DBGDBCR_BYTE_ADDR_SHIFT
#define DBGDBCR_BYTE_ADDR_SHIFT 5 |
◆ DBGDBCR_MEANING_ADDR_MISMATCH
#define DBGDBCR_MEANING_ADDR_MISMATCH 0x4 |
◆ DBGDBCR_MEANING_MASK
#define DBGDBCR_MEANING_MASK 0x7 |
◆ DBGDBCR_MEANING_SHIFT
#define DBGDBCR_MEANING_SHIFT 20 |
◆ DBGDSCR_MONITOR_MODE_EN
#define DBGDSCR_MONITOR_MODE_EN 0x8000 |
◆ GDB_READALL_PACKET_SIZE
#define GDB_READALL_PACKET_SIZE (42 * 8) |
◆ IFSR_DEBUG_EVENT
#define IFSR_DEBUG_EVENT 0x2 |
◆ SPSR_ISETSTATE_ARM
#define SPSR_ISETSTATE_ARM 0x0 |
◆ SPSR_ISETSTATE_JAZELLE
#define SPSR_ISETSTATE_JAZELLE 0x2 |
◆ SPSR_J
◆ SPSR_REG_IDX
◆ SPSR_T
◆ AARCH32_GDB_REG
Enumerator |
---|
R0 | |
R1 | |
R2 | |
R3 | |
R4 | |
R5 | |
R6 | |
R7 | |
R8 | |
R9 | |
R10 | |
R11 | |
R12 | |
R13 | |
LR | |
PC | |
SPSR | |
GDB_NUM_REGS | |