st,stm32-dma-v2¶
Vendor: STMicroelectronics
Description¶
These nodes are “dma” bus nodes.
STM32 DMA controller (V2)
The STM32 DMA is a general-purpose direct memory access controller
capable of supporting 5 or 6 or 7 or 8 independent DMA channels.
Each channel can have up to 8 requests.
DMA clients connected to the STM32 DMA controller must use the format
described in the dma.txt file, using a four-cell specifier for each
channel: a phandle to the DMA controller plus the following four integer cells:
1. channel: the dma stream from 1 to <dma-requests>
2. slot: DMA periph request ID
3. channel-config: A 32bit mask specifying the DMA channel configuration
which is device dependent:
-bit 6-7 : Direction (see dma.h)
0x0: MEM to MEM
0x1: MEM to PERIPH
0x2: PERIPH to MEM
0x3: reserved for PERIPH to PERIPH
-bit 9 : Peripheral Increment Address
0x0: no address increment between transfers
0x1: increment address between transfers
-bit 10 : Memory Increment Address
0x0: no address increment between transfers
0x1: increment address between transfers
-bit 11-12 : Peripheral data size
0x0: Byte (8 bits)
0x1: Half-word (16 bits)
0x2: Word (32 bits)
0x3: reserved
-bit 13-14 : Memory data size
0x0: Byte (8 bits)
0x1: Half-word (16 bits)
0x2: Word (32 bits)
0x3: reserved
-bit 15: Reserved
-bit 16-17 : Priority level
0x0: low
0x1: medium
0x2: high
0x3: very high
4. Features. Not used. Kept for binding compatibility with "st,stm32-dma-v1"
Example of dma node for stm32wb55x
dma2: dma-controller@40020400 {
compatible = "st,stm32-dma-v2";
...
dma-requests = <7>;
status = "disabled";
label = "DMA_2";
};
For the client part, example for stm32l476 on DMA1 instance
Tx using channel 3 with request 1
Rx using channel 2 with request 1
spi1 {
compatible = "st,stm32-spi";
dmas = <&dma1 3 1 0x20440 0x00>,
<&dma1 2 1 0x20480 0x00>;
dma-names = "tx", "rx";
};
Properties¶
Properties not inherited from the base binding file.
Name |
Type |
Details |
|---|---|---|
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offset in the table of channels when mapping to a DMAMUX for 1st dma instance, offset is 0, for 2nd dma instance, offset is the nb of dma channels of the 1st dma, for 3rd dma instance, offset is the nb of dma channels of the 2nd dma plus the nb of dma channels of the 1st dma instance, etc.
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Number of items to expect in a DMA specifier
This property is required. Constant value: |
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Bitmask of available DMA channels in ascending order that are not reserved by firmware and are available to the kernel. i.e. first channel corresponds to LSB.
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Number of DMA channels supported by the controller
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Number of DMA request signals supported by the controller.
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Deprecated properties not inherited from the base binding file.
(None)
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “st,stm32-dma-v2” compatible.
Name |
Type |
Details |
|---|---|---|
|
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register space
This property is required. See Important properties for more information. |
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interrupts for device
This property is required. See Important properties for more information. |
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Human readable string describing the device (used as device_get_binding() argument)
This property is required. See Important properties for more information. |
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indicates the operational status of a device
Legal values: See Important properties for more information. |
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compatible strings
This property is required. See Important properties for more information. |
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name of each register space
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extended interrupt specifier for device
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name of each interrupt
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phandle to interrupt controller node
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Clock gate information
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name of each clock
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number of address cells in reg property
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number of size cells in reg property
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DMA channels specifiers
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Provided names of DMA channel specifiers
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IO channels specifiers
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Provided names of IO channel specifiers
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Specifier cell names¶
dma cells: channel, slot, channel-config, features