st,stm32wl-rcc

Vendor: STMicroelectronics

Description

STM32WL Reset and Clock controller node.
For more description confere st,stm32-rcc.yaml

Properties

Properties not inherited from the base binding file.

Name

Type

Details

ahb3-prescaler

int

HCLK3 shared prescaler (AHB3, Flash memory, SRAM1 and SRAM2).
(A.K.A SHDHPRE)

Legal values: 1, 2, 4, 8, 16, 32, 64, 128, 256, 512

cpu1-prescaler

int

CPU1 prescaler. Sets a HCLK1 frequency (feeding Cortex-M Systick)
lower than SYSCLK frequency (actual core frequency).
Zephyr doesn't make a difference today between these two clocks.
Changing this prescaler is not allowed until it is made possible to
use them independently in Zephyr clock subsystem.
HCLK1 clocks CPU1, AHB1, AHB2, AHB3 and SRAM1.

Legal values: 1

cpu2-prescaler

int

CPU2 prescaler. Sets HCLK2 frequency which clocks CPU2.
(A.K.A C2HPRE)

Legal values: 1, 2, 4, 8, 16, 32, 64, 128, 256, 512

#clock-cells

int

Number of items to expect in a Clock specifier

This property is required.

Constant value: 2

clock-frequency

int

default frequency in Hz for clock output

apb1-prescaler

int

Legal values: 1, 2, 4, 8, 16

apb2-prescaler

int

Legal values: 1, 2, 4, 8, 16

Specifier cell names

  • clock cells: bus, bits