-
CONFIG_CLOCK_STM32_PLL3_ENABLE
¶
Enable PLL3
Type: bool
Help¶
Enable PLL3. It is used to generate the kernel clock for some peripherals.
Direct dependencies¶
SOC_SERIES_STM32H7X
&& !CLOCK_CONTROL_STM32_HAS_DTS
&& !SOC_SERIES_STM32MP1X
&& CLOCK_CONTROL_STM32_CUBE
&& CLOCK_CONTROL
(Includes any dependencies from ifs and menus.)
Defaults¶
No defaults. Implicitly defaults to n
.
Kconfig definition¶
At <Zephyr>/drivers/clock_control/Kconfig.stm32h7:109
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:32
→ <Zephyr>/drivers/Kconfig:54
→ <Zephyr>/drivers/clock_control/Kconfig:25
→ <Zephyr>/drivers/clock_control/Kconfig.stm32:153
Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control
config CLOCK_STM32_PLL3_ENABLE
bool "Enable PLL3"
depends on SOC_SERIES_STM32H7X && !CLOCK_CONTROL_STM32_HAS_DTS && !SOC_SERIES_STM32MP1X && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL
help
Enable PLL3. It is used to generate the kernel clock for some peripherals.
(The ‘depends on’ condition includes propagated dependencies from ifs and menus.)