Help¶

APB2 High speed clock (PCLK2) prescaler, allowed values:
1, 2, 4, 8, 16

Direct dependencies¶

!SOC_SERIES_STM32F0X && !SOC_SERIES_STM32G0X && !SOC_SERIES_STM32H7X && !CLOCK_CONTROL_STM32_HAS_DTS && !SOC_SERIES_STM32MP1X && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL

(Includes any dependencies from ifs and menus.)

Default¶

1

Kconfig definition¶

At <Zephyr>/drivers/clock_control/Kconfig.stm32:180

Included via <Zephyr>/Kconfig:8 → <Zephyr>/Kconfig.zephyr:32 → <Zephyr>/drivers/Kconfig:54 → <Zephyr>/drivers/clock_control/Kconfig:25

Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control

config CLOCK_STM32_APB2_PRESCALER
    int "APB2 prescaler"
    range 1 16
    default 1
    depends on !SOC_SERIES_STM32F0X && !SOC_SERIES_STM32G0X && !SOC_SERIES_STM32H7X && !CLOCK_CONTROL_STM32_HAS_DTS && !SOC_SERIES_STM32MP1X && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL
    help
      APB2 High speed clock (PCLK2) prescaler, allowed values:
      1, 2, 4, 8, 16

(The ‘depends on’ condition includes propagated dependencies from ifs and menus.)