Help¶

Core Domain Clock (OSC_CLK) Generator PLL frequency,
allowed values: From 10Mhz to 100Mhz.

Direct dependencies¶

SOC_FAMILY_NPCX && CLOCK_CONTROL

(Includes any dependencies from ifs and menus.)

Default¶

48000000

Kconfig definition¶

At <Zephyr>/drivers/clock_control/Kconfig.npcx:12

Included via <Zephyr>/Kconfig:8 → <Zephyr>/Kconfig.zephyr:32 → <Zephyr>/drivers/Kconfig:54 → <Zephyr>/drivers/clock_control/Kconfig:43

Menu path: (Top) → Device Drivers → Hardware clock controller support

config CLOCK_NPCX_OSC_CYCLES_PER_SEC
    int "CDCG PLL frequency"
    range 10000000 100000000
    default 48000000
    depends on SOC_FAMILY_NPCX && CLOCK_CONTROL
    help
      Core Domain Clock (OSC_CLK) Generator PLL frequency,
      allowed values: From 10Mhz to 100Mhz.

(The ‘depends on’ condition includes propagated dependencies from ifs and menus.)