microchip,xec-qmspi-ldma

Vendor: Microchip Technology Inc.

Description

These nodes are “spi” bus nodes.

Microchip XEC QMSPI controller with local DMA

Properties

Properties not inherited from the base binding file.

Name

Type

Details

girqs

array

 
An array of integers encoding each interrupt signal connection.
This information includes the aggregated GIRQ number, GIRQ bit
position, aggregated GIRQ NVIC connection, and direct NVIC
connection of the GIRQ bit.

This property is required.

pinctrl-0

phandles

 
Pin configuration/s for the first state. Content is specific to the
selected pin controller driver implementation.

This property is required.

pinctrl-names

string-array

 
Names for the provided states. The number of names needs to match the
number of states.

This property is required.

lines

int

 
QMSPI data lines 1, 2, or 4. 1 data line is full-duplex
MOSI and MISO or half-duplex on MOSI only. Lines set to 2
or 4 indicate dual or quad I/O modes.
Defaults to 1 for full duplex driver's support for full-duplex spi.

Legal values: 1, 2, 4

chip-select

int

 
Use QMSPI CS0# or CS1#. Port 0 supports both chip selects.
Ports 1 and 2 implement CS0# only. Defaults to CS0#.

dcsckon

int

 
Delay in QMSPI main clocks from CS# assertion to first clock edge.
If not present use hardware default value. Refer to chip documentation
for QMSPI input clock frequency.

dckcsoff

int

 
Delay in QMSPI main clocks from last clock edge to CS# de-assertion.
If not present use hardware default value. Refer to chip documentation
for QMSPI input clock frequency.

dldh

int

 
Delay in QMSPI main clocks from CS# de-assertion to driving HOLD#
and WP#. If not present use hardware default value. Refer to chip
documentation for QMSPI input clock frequency.

dcsda

int

 
Delay in QMSPI main clocks from CS# de-assertion to CS# assertion.
If not present use hardware default value. Refer to chip documentation
for QMSPI input clock frequency.

cs1-freq

int

 
Allows different frequencies for CS#0 and CS1# devices. This applies
to ports implementing CS1#.

tctradj

int

 
An optional signed 8-bit value for adjusting the QMSPI control signal
timing tap.

tsckadj

int

 
An optional signed 8-bit value for adjusting the QMSPI clock signal
timing tap.

clock-frequency

int

 
Clock frequency the SPI peripheral is being driven at, in Hz.

cs-gpios

phandle-array

 
An array of chip select GPIOs to use. Each element
in the array specifies a GPIO. The index in the array
corresponds to the child node that the CS gpio controls.

Example:

  spi@... {
          cs-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>,
                        <&gpio1 10 GPIO_ACTIVE_LOW>,
                        ...;

          spi-device@0 {
                  reg = <0>;
                  ...
          };
          spi-device@1 {
                  reg = <1>;
                  ...
          };
          ...
  };

The child node "spi-device@0" specifies a SPI device with
chip select controller gpio0, pin 23, and devicetree
GPIO flags GPIO_ACTIVE_LOW. Similarly, "spi-device@1" has CS GPIO
controller gpio1, pin 10, and flags GPIO_ACTIVE_LOW. Additional
devices can be configured in the same way.

If unsure about the flags cell, GPIO_ACTIVE_LOW is generally a safe
choice for a typical "CSn" pin. GPIO_ACTIVE_HIGH may be used if
intervening hardware inverts the signal to the peripheral device or
the line itself is active high.

If this property is not defined, no chip select GPIOs are set.
SPI controllers with dedicated CS pins do not need to define
the cs-gpios property.

pinctrl-1

phandles

 
Pin configuration/s for the second state. See pinctrl-0.

pinctrl-2

phandles

 
Pin configuration/s for the third state. See pinctrl-0.

pinctrl-3

phandles

 
Pin configuration/s for the fourth state. See pinctrl-0.

pinctrl-4

phandles

 
Pin configuration/s for the fifth state. See pinctrl-0.