infineon,cat1-uart

Vendor: Infineon Technologies

Description

These nodes are “uart” bus nodes.

Infineon CAT1 UART

Properties

Properties not inherited from the base binding file.

Name

Type

Details

pinctrl-0

phandles

 
PORT pin configuration for TX, RX, RTS, CTS signals.
We expect that the phandles will reference pinctrl nodes. These
nodes will have a nodelabel that matches the Infineon SoC Pinctrl
defines and be of the form p<port>_<pin><peripheral inst>_<signal>.

Examples
   use TX, RX
   pinctrl-0 = <&p5_1_scb5_uart_tx &p5_0_scb5_uart_rx>;

   use RX only
   pinctrl-0 = <&p5_0_scb5_uart_rx>;

   use TX, RX, RTS, CTS
   pinctrl-0 = <&p3_1_scb2_uart_tx &p3_0_scb2_uart_rx
                &p3_2_scb2_uart_rts &p3_3_scb2_uart_cts>;

This property is required.

pinctrl-names

string-array

 
Names for the provided states. The number of names needs to match the
number of states.

This property is required.

clock-frequency

int

 
Clock frequency information for UART operation

current-speed

int

 
Initial baud rate setting for UART

hw-flow-control

boolean

 
Set to enable RTS/CTS flow control at boot time

parity

string

 
Configures the parity of the adapter. Enumeration id 0 for none, 1 for odd
and 2 for even parity. Default to none if not specified.

Legal values: 'none', 'odd', 'even'

stop-bits

string

 
Sets the number of stop bits.

Legal values: '0_5', '1', '1_5', '2'

data-bits

int

 
Sets the number of data bits.

Legal values: 5, 6, 7, 8, 9

pinctrl-1

phandles

 
Pin configuration/s for the second state. See pinctrl-0.

pinctrl-2

phandles

 
Pin configuration/s for the third state. See pinctrl-0.

pinctrl-3

phandles

 
Pin configuration/s for the fourth state. See pinctrl-0.

pinctrl-4

phandles

 
Pin configuration/s for the fifth state. See pinctrl-0.