xlnx,pinctrl-zynqmp
Vendor: Xilinx
Description
Xilinx ZynqMP SoC pinctrl node. It allows configuration of pin assignments
for the supported peripherals.
See Zynq UltraScale+ Devices Register Reference (UG1087) for details regarding
valid pin assignments
Properties
Top level properties
These property descriptions apply to “xlnx,pinctrl-zynqmp” nodes themselves. This page also describes child node properties in the following sections.
Properties not inherited from the base binding file.
(None)
Deprecated properties not inherited from the base binding file.
(None)
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “xlnx,pinctrl-zynqmp” compatible.
Name |
Type |
Details |
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indicates the operational status of a device
Legal values: See Important properties for more information. |
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compatible strings
This property is required. See Important properties for more information. |
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register space
See Important properties for more information. |
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name of each register space
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interrupts for device
See Important properties for more information. |
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extended interrupt specifier for device
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name of each interrupt
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phandle to interrupt controller node
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Human readable string describing the device (used as device_get_binding() argument)
See Important properties for more information. This property is deprecated. |
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Clock gate information
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name of each clock
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number of address cells in reg property
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number of size cells in reg property
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DMA channels specifiers
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Provided names of DMA channel specifiers
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IO channels specifiers
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Provided names of IO channel specifiers
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mailbox / IPM channels specifiers
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Provided names of mailbox / IPM channel specifiers
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Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
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Power domain the device belongs to.
The device will be notified when the power domain it belongs to is either
suspended or resumed.
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Automatically configure the device for runtime power management after the
init function runs.
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Grandchild node properties
Name |
Type |
Details |
|---|---|---|
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Pin assignments for the selected group
This property is required. |
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disable any pin bias
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high impedance mode ("third-state", "floating")
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latch weakly
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enable pull-up resistor
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enable pull-down resistor
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use pin's default pull state
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drive actively high and low
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drive with open drain (hardware AND)
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drive with open source (hardware OR)
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maximum sink or source current in mA
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maximum sink or source current in μA
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enable input on pin (e.g. enable an input buffer, no effect on output)
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disable input on pin (e.g. disable an input buffer, no effect on output)
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enable schmitt-trigger mode
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disable schmitt-trigger mode
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Takes the debounce time in μsec, as argument or 0 to disable debouncing
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select between different power supplies
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enable low power mode
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disable low power mode
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disable output on a pin (e.g. disable an output buffer)
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enable output on a pin without actively driving it (e.g. enable an output
buffer)
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set the pin to output mode with low level
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set the pin to output mode with high level
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indicate this is sleep related state which will be programmed into
the registers for the sleep state
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set the slew rate
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This affects the expected clock skew on input pins and the delay
before latching a value to an output pin. Typically indicates how
many double-inverters are used to delay the signal.
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