seeed,xiao-gpio

Vendor: Seeed Technology Co., Ltd

Description

GPIO pins exposed on Seeeduino Xiao (and compatible devices) headers.

The Seeeeduino Xiao layout provides two headers, along opposite
edges of the board.

Proceeding counter-clockwise:
* A 7-pin Digital/Analog Input header.  This has input signals
  labeled from 0 at the top through 6 at the bottom.
* An 7-pin header Power and Digital/Analog Input header.  This
  has three power pins, followed by four inputs labeled 10 at the
  top through 7 at the bottom.

This binding provides a nexus mapping for 10 pins where parent pins 0
through 10 correspond to D0 through D10, as depicted below:

    0 D0                     5V   -
    1 D1                     GND  -
    2 D2                     3V3  -
    3 D3                     D10 10
    4 A4                     D9   9
    5 D5                     D8   8
    6 D6                     D7   7

Properties

Properties not inherited from the base binding file.

Name

Type

Details

gpio-map

compound

This property is required.

gpio-map-mask

compound

gpio-map-pass-thru

compound

#gpio-cells

int

Number of items to expect in a GPIO specifier

This property is required.