:orphan:
.. raw:: html
.. dtcompatible:: nxp,imx-flexspi
.. _dtbinding_nxp_imx_flexspi:
nxp,imx-flexspi
###############
Vendor: :ref:`NXP Semiconductors `
Description
***********
These nodes are "spi" bus nodes.
.. code-block:: none
NXP FlexSPI controller
Properties
**********
Top level properties
====================
These property descriptions apply to "nxp,imx-flexspi"
nodes themselves. This page also describes child node
properties in the following sections.
.. tabs::
.. group-tab:: Node specific properties
Properties not inherited from the base binding file.
.. list-table::
:widths: 1 1 4
:header-rows: 1
* - Name
- Type
- Details
* - ``ahb-bufferable``
- ``boolean``
- .. code-block:: none
Enable AHB bufferable write access by setting register field
AHBCR[BUFFERABLEEN].
* - ``ahb-cacheable``
- ``boolean``
- .. code-block:: none
Enable AHB cacheable read access by setting register field
AHBCR[CACHEABLEEN].
* - ``ahb-prefetch``
- ``boolean``
- .. code-block:: none
Enable AHB read prefetch by setting register field AHBCR[PREFETCHEN].
* - ``ahb-read-addr-opt``
- ``boolean``
- .. code-block:: none
Remove burst start address alignment limitation by setting register
field AHBCR[READADDROPT].
* - ``combination-mode``
- ``boolean``
- .. code-block:: none
Combine port A and port B data pins to support octal mode access by
setting register field MCR0[COMBINATIONEN].
* - ``sck-differential-clock``
- ``boolean``
- .. code-block:: none
Enable/disable SCKB pad use as SCKA differential clock output,
when enabled, Port B flash access is not available.
* - ``rx-clock-source``
- ``int``
- .. code-block:: none
Source clock for flash read. See the RXCLKSRC field in register MCR0.
The default corresponds to the reset value of the register field.
Legal values: ``0``, ``1``, ``2``, ``3``
* - ``rx-buffer-config``
- ``array``
- .. code-block:: none
Array of tuples to configure AHB RX buffers. Format is the following:
. Pass multiple tuples to configure
multiple RX buffers (up to maximum supported by SOC).
The tuple fields correspond to the following register bitfields:
prefetch: AHBRXBUFxCRx[PREFETCH]
priority: AHBRXBUFxCRx[PRIORITY]
master_id: AHBRXBUFxCRx[MSTRID]
buf_size: AHBRXBUFxCRx[BUFSZ]
* - ``clock-frequency``
- ``int``
- .. code-block:: none
Clock frequency the SPI peripheral is being driven at, in Hz.
* - ``cs-gpios``
- ``phandle-array``
- .. code-block:: none
An array of chip select GPIOs to use. Each element
in the array specifies a GPIO. The index in the array
corresponds to the child node that the CS gpio controls.
Example:
spi@... {
cs-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>,
<&gpio1 10 GPIO_ACTIVE_LOW>,
...;
spi-device@0 {
reg = <0>;
...
};
spi-device@1 {
reg = <1>;
...
};
...
};
The child node "spi-device@0" specifies a SPI device with
chip select controller gpio0, pin 23, and devicetree
GPIO flags GPIO_ACTIVE_LOW. Similarly, "spi-device@1" has CS GPIO
controller gpio1, pin 10, and flags GPIO_ACTIVE_LOW. Additional
devices can be configured in the same way.
If unsure about the flags cell, GPIO_ACTIVE_LOW is generally a safe
choice for a typical "CSn" pin. GPIO_ACTIVE_HIGH may be used if
intervening hardware inverts the signal to the peripheral device or
the line itself is active high.
If this property is not defined, no chip select GPIOs are set.
SPI controllers with dedicated CS pins do not need to define
the cs-gpios property.
* - ``pinctrl-0``
- ``phandles``
- .. code-block:: none
Pin configuration/s for the first state. Content is specific to the
selected pin controller driver implementation.
* - ``pinctrl-1``
- ``phandles``
- .. code-block:: none
Pin configuration/s for the second state. See pinctrl-0.
* - ``pinctrl-2``
- ``phandles``
- .. code-block:: none
Pin configuration/s for the third state. See pinctrl-0.
* - ``pinctrl-3``
- ``phandles``
- .. code-block:: none
Pin configuration/s for the fourth state. See pinctrl-0.
* - ``pinctrl-4``
- ``phandles``
- .. code-block:: none
Pin configuration/s for the fifth state. See pinctrl-0.
* - ``pinctrl-names``
- ``string-array``
- .. code-block:: none
Names for the provided states. The number of names needs to match the
number of states.
.. group-tab:: Deprecated node specific properties
Deprecated properties not inherited from the base binding file.
(None)
.. group-tab:: Base properties
Properties inherited from the base binding file, which defines
common properties that may be set on many nodes. Not all of these
may apply to the "nxp,imx-flexspi" compatible.
.. list-table::
:widths: 1 1 4
:header-rows: 1
* - Name
- Type
- Details
* - ``reg``
- ``array``
- .. code-block:: none
register space
This property is **required**.
See :ref:`dt-important-props` for more information.
* - ``interrupts``
- ``array``
- .. code-block:: none
interrupts for device
This property is **required**.
See :ref:`dt-important-props` for more information.
* - ``#address-cells``
- ``int``
- .. code-block:: none
number of address cells in reg property
This property is **required**.
Constant value: ``1``
* - ``#size-cells``
- ``int``
- .. code-block:: none
number of size cells in reg property
This property is **required**.
* - ``status``
- ``string``
- .. code-block:: none
indicates the operational status of a device
Legal values: ``'ok'``, ``'okay'``, ``'disabled'``, ``'reserved'``, ``'fail'``, ``'fail-sss'``
See :ref:`dt-important-props` for more information.
* - ``compatible``
- ``string-array``
- .. code-block:: none
compatible strings
This property is **required**.
See :ref:`dt-important-props` for more information.
* - ``reg-names``
- ``string-array``
- .. code-block:: none
name of each register space
* - ``interrupts-extended``
- ``compound``
- .. code-block:: none
extended interrupt specifier for device
* - ``interrupt-names``
- ``string-array``
- .. code-block:: none
name of each interrupt
* - ``interrupt-parent``
- ``phandle``
- .. code-block:: none
phandle to interrupt controller node
* - ``label``
- ``string``
- .. code-block:: none
Human readable string describing the device (used as device_get_binding() argument)
See :ref:`dt-important-props` for more information.
This property is **deprecated**.
* - ``clocks``
- ``phandle-array``
- .. code-block:: none
Clock gate information
* - ``clock-names``
- ``string-array``
- .. code-block:: none
name of each clock
* - ``dmas``
- ``phandle-array``
- .. code-block:: none
DMA channels specifiers
* - ``dma-names``
- ``string-array``
- .. code-block:: none
Provided names of DMA channel specifiers
* - ``io-channels``
- ``phandle-array``
- .. code-block:: none
IO channels specifiers
* - ``io-channel-names``
- ``string-array``
- .. code-block:: none
Provided names of IO channel specifiers
* - ``mboxes``
- ``phandle-array``
- .. code-block:: none
mailbox / IPM channels specifiers
* - ``mbox-names``
- ``string-array``
- .. code-block:: none
Provided names of mailbox / IPM channel specifiers
* - ``wakeup-source``
- ``boolean``
- .. code-block:: none
Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
* - ``power-domain``
- ``phandle``
- .. code-block:: none
Power domain the device belongs to.
The device will be notified when the power domain it belongs to is either
suspended or resumed.
* - ``zephyr,pm-device-runtime-auto``
- ``boolean``
- .. code-block:: none
Automatically configure the device for runtime power management after the
init function runs.
Child node properties
=====================
.. list-table::
:widths: 1 1 4
:header-rows: 1
* - Name
- Type
- Details
* - ``cs-interval-unit``
- ``int``
- .. code-block:: none
Chip select interval units, in serial clock cycles. See the
CSINTERVALUNIT field in registers FLASHA1CR0 through FLASHB2CR0. The
default corresponds to the reset value of the register field.
Default value: ``1``
Legal values: ``1``, ``256``
* - ``cs-interval``
- ``int``
- .. code-block:: none
Minimum interval between chip select deassertion and assertion. See the
CSINTERVAL field in registers FLASHA1CR0 through FLASHB2CR0. The
default corresponds to the reset value of the register field.
* - ``cs-setup-time``
- ``int``
- .. code-block:: none
Chip select setup time, in serial clock cycles. See the TCSS field in
registers FLASHA1CR0 through FLASHB2CR0. The default corresponds to the
reset value of the register field.
Default value: ``3``
* - ``cs-hold-time``
- ``int``
- .. code-block:: none
Chip select hold time, in serial clock cycles. See the TCSH field in
registers FLASHA1CR0 through FLASHB2CR0. The default corresponds to the
reset value of the register field.
Default value: ``3``
* - ``data-valid-time``
- ``int``
- .. code-block:: none
Data valid time, in nanoseconds. See the registers DLLACR through
DLLBCR.
* - ``column-space``
- ``int``
- .. code-block:: none
Column address bit width. Set to zero if the flash does not support
column address. See the CAS field in registers FLASHA1CR0 through
FLASHB2CR0. The default corresponds to the reset value of the register
field.
* - ``word-addressable``
- ``boolean``
- .. code-block:: none
Don't transmit the least significant address bit when the flash is word
addressable. See the WA field in registers FLASHA1CR0 through
FLASHB2CR0.
* - ``ahb-write-wait-unit``
- ``int``
- .. code-block:: none
AHB write wait interval units, in AHB clock cycles. See the AWRWAITUNIT
field in registers FLASHA1CR2 through FLASHB2CR2. The default
corresponds to the reset value of the register field.
Default value: ``2``
Legal values: ``2``, ``8``, ``32``, ``128``, ``512``, ``2048``, ``8192``, ``32768``
* - ``ahb-write-wait-interval``
- ``int``
- .. code-block:: none
Time to wait between AHB triggered command sequences. See the AWRWAIT
field in registers FLASHA1CR2 through FLASHB2CR2. The default
corresponds to the reset value of the register field.
* - ``reg``
- ``array``
- .. code-block:: none
register space
This property is **required**.
See :ref:`dt-important-props` for more information.
* - ``spi-max-frequency``
- ``int``
- .. code-block:: none
Maximum clock frequency of device's SPI interface in Hz
This property is **required**.
* - ``duplex``
- ``int``
- .. code-block:: none
Duplex mode, full or half. By default it's always full duplex thus 0
as this is, by far, the most common mode.
Use the macros not the actual enum value, here is the concordance
list (see dt-bindings/spi/spi.h)
0 SPI_FULL_DUPLEX
2048 SPI_HALF_DUPLEX
Legal values: ``0``, ``2048``
* - ``frame-format``
- ``int``
- .. code-block:: none
Motorola or TI frame format. By default it's always Motorola's,
thus 0 as this is, by far, the most common format.
Use the macros not the actual enum value, here is the concordance
list (see dt-bindings/spi/spi.h)
0 SPI_FRAME_FORMAT_MOTOROLA
32768 SPI_FRAME_FORMAT_TI
Legal values: ``0``, ``32768``
* - ``spi-cpol``
- ``boolean``
- .. code-block:: none
SPI clock polarity which indicates the clock idle state.
If it is used, the clock idle state is logic high; otherwise, low.
* - ``spi-cpha``
- ``boolean``
- .. code-block:: none
SPI clock phase that indicates on which edge data is sampled.
If it is used, data is sampled on the second edge; otherwise, on the first edge.
* - ``spi-hold-cs``
- ``boolean``
- .. code-block:: none
In some cases, it is necessary for the master to manage SPI chip select
under software control, so that multiple spi transactions can be performed
without releasing it. A typical use case is variable length SPI packets
where the first spi transaction reads the length and the second spi transaction
reads length bytes.
* - ``status``
- ``string``
- .. code-block:: none
indicates the operational status of a device
Legal values: ``'ok'``, ``'okay'``, ``'disabled'``, ``'reserved'``, ``'fail'``, ``'fail-sss'``
See :ref:`dt-important-props` for more information.
* - ``compatible``
- ``string-array``
- .. code-block:: none
compatible strings
This property is **required**.
See :ref:`dt-important-props` for more information.
* - ``reg-names``
- ``string-array``
- .. code-block:: none
name of each register space
* - ``interrupts``
- ``array``
- .. code-block:: none
interrupts for device
See :ref:`dt-important-props` for more information.
* - ``interrupts-extended``
- ``compound``
- .. code-block:: none
extended interrupt specifier for device
* - ``interrupt-names``
- ``string-array``
- .. code-block:: none
name of each interrupt
* - ``interrupt-parent``
- ``phandle``
- .. code-block:: none
phandle to interrupt controller node
* - ``label``
- ``string``
- .. code-block:: none
Human readable string describing the device (used as device_get_binding() argument)
See :ref:`dt-important-props` for more information.
This property is **deprecated**.
* - ``clocks``
- ``phandle-array``
- .. code-block:: none
Clock gate information
* - ``clock-names``
- ``string-array``
- .. code-block:: none
name of each clock
* - ``#address-cells``
- ``int``
- .. code-block:: none
number of address cells in reg property
* - ``#size-cells``
- ``int``
- .. code-block:: none
number of size cells in reg property
* - ``dmas``
- ``phandle-array``
- .. code-block:: none
DMA channels specifiers
* - ``dma-names``
- ``string-array``
- .. code-block:: none
Provided names of DMA channel specifiers
* - ``io-channels``
- ``phandle-array``
- .. code-block:: none
IO channels specifiers
* - ``io-channel-names``
- ``string-array``
- .. code-block:: none
Provided names of IO channel specifiers
* - ``mboxes``
- ``phandle-array``
- .. code-block:: none
mailbox / IPM channels specifiers
* - ``mbox-names``
- ``string-array``
- .. code-block:: none
Provided names of mailbox / IPM channel specifiers
* - ``wakeup-source``
- ``boolean``
- .. code-block:: none
Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
* - ``power-domain``
- ``phandle``
- .. code-block:: none
Power domain the device belongs to.
The device will be notified when the power domain it belongs to is either
suspended or resumed.
* - ``zephyr,pm-device-runtime-auto``
- ``boolean``
- .. code-block:: none
Automatically configure the device for runtime power management after the
init function runs.
* - ``supply-gpios``
- ``phandle-array``
- .. code-block:: none
GPIO specifier that controls power to the device.
This property should be provided when the device has a dedicated
switch that controls power to the device. The supply state is
entirely the responsibility of the device driver.
Contrast with vin-supply.
* - ``vin-supply``
- ``phandle``
- .. code-block:: none
Reference to the regulator that controls power to the device.
The referenced devicetree node must have a regulator compatible.
This property should be provided when device power is supplied
by a shared regulator. The supply state is dependent on the
request status of all devices fed by the regulator.
Contrast with supply-gpios. If both properties are provided
then the regulator must be requested before the supply GPIOS is
set to an active state, and the supply GPIOS must be set to an
inactive state before releasing the regulator.
* - ``jedec-id``
- ``uint8-array``
- .. code-block:: none
JEDEC ID as manufacturer ID, memory type, memory density
* - ``size``
- ``int``
- .. code-block:: none
flash capacity in bits
* - ``sfdp-bfp``
- ``uint8-array``
- .. code-block:: none
Contains the 32-bit words in little-endian byte order from the
JESD216 Serial Flash Discoverable Parameters Basic Flash
Parameters table. This provides flash-specific configuration
information in cases were runtime retrieval of SFDP data
is not desired.
* - ``quad-enable-requirements``
- ``string``
- .. code-block:: none
Quad Enable Requirements value from JESD216 BFP DW15.
Use NONE if the device detects 1-1-4 and 1-4-4 modes by the
instruction. Use S1B6 if QE is bit 6 of the first status register
byte, and can be configured by reading then writing one byte with
RDSR and WRSR. For other fields see the specification.
Legal values: ``'NONE'``, ``'S2B1v1'``, ``'S1B6'``, ``'S2B7'``, ``'S2B1v4'``, ``'S2B1v5'``, ``'S2B1v6'``
* - ``enter-4byte-addr``
- ``int``
- .. code-block:: none
Enter 4-Byte Addressing value from JESD216 BFP DW16
This property is ignored if the device is configured to use SFDP data
from the sfdp-bfp property (CONFIG_SPI_NOR_SFDP_DEVICETREE) or to read
SFDP properties at runtime (CONFIG_SPI_NOR_SFDP_RUNTIME).
For CONFIG_SPI_NOR_SFDP_MINIMAL this is the 8-bit value from bits 31:24
of DW16 identifying ways a device can be placed into 4-byte addressing
mode. If provided as a non-zero value the driver assumes that 4-byte
addressing is require to access the full address range, and
automatically puts the device into 4-byte address mode when the device
is initialized.
* - ``page-size``
- ``int``
- .. code-block:: none
Number of bytes in a page from JESD216 BFP DW11
This property is only used in the CONFIG_SPI_NOR_SFDP_MINIMAL configuration.
It is ignored if the device is configured to use SFDP data
from the sfdp-bfp property (CONFIG_SPI_NOR_SFDP_DEVICETREE) or
if the SFDP parameters are read from the device at
runtime (CONFIG_SPI_NOR_SFDP_RUNTIME).
The default value is 256 bytes if the value is not specified.