ite,enhance-i2c

Vendor: ITE Tech. Inc.

Description

These nodes are “i2c” bus nodes.

ITE enhance I2C

Properties

Properties not inherited from the base binding file.

Name

Type

Details

prescale-scl-low

int

This option is used to configure the I2C speed prescaler for
the SCL low period. When set to >= 1, it will increase the
low period of the SCL clock and so reduce the signal frequency.
The resulting SCL cycle time is given by the following formula:
SCL cycle = 2 * (psr + prescale_tweak + 2) *
            SMBus clock cycle

port-num

int

Ordinal identifying the port 0 = SMB_CHANNEL_A, 1 = SMB_CHANNEL_B, 2 = SMB_CHANNEL_C, 3 = I2C_CHANNEL_D, 4 = I2C_CHANNEL_E, 5 = I2C_CHANNEL_F,

This property is required.

Legal values: 0, 1, 2, 3, 4, 5

scl-gpios

phandle-array

The SCL pin for the selected port.

This property is required.

sda-gpios

phandle-array

The SDA pin for the selected port.

This property is required.

clock-gate-offset

int

The clock gate offsets combine the register offset from
ECPM_BASE and the mask within that register into one value.

This property is required.

pinctrl-0

phandles

Pin configuration/s for the first state. Content is specific to the
selected pin controller driver implementation.

This property is required.

pinctrl-names

string-array

Names for the provided states. The number of names needs to match the
number of states.

This property is required.

clock-frequency

int

Initial clock frequency in Hz

pinctrl-1

phandles

Pin configuration/s for the second state. See pinctrl-0.

pinctrl-2

phandles

Pin configuration/s for the third state. See pinctrl-0.

pinctrl-3

phandles

Pin configuration/s for the fourth state. See pinctrl-0.

pinctrl-4

phandles

Pin configuration/s for the fifth state. See pinctrl-0.