###################### Floating-Point Support ###################### TF-M adds several configuration flags to control Floating point (FP) [1]_ support in TF-M Secure Processing Environment (SPE) and Non Secure Processing Environment (NSPE). * Support FP in SPE or NSPE. * Support FP Application Binary Interface (ABI) [2]_ types: software, hardware. SPE and NSPE shall use the same FP ABI type. * Support lazy stacking enable/disable in SPE only, NSPE is not allowed to enable/disable this feature. * Support GNU Arm Embedded Toolchain [3]_. ``GNU Arm Embedded Toolchain 10.3- 2021.10`` and later version shall be used to mitigate VLLDM instruction security vulnerability [4]_. * Support Inter-Process Communication (IPC) [5]_ model in TF-M, and doesn't support LIBRARY or SFN model. * Support Armv8.0-M mainline. * Support isolation level 1,2,3. * Does not support use FPU in First-Level Interrupt Handling (FLIH) [6]_ at current stage. Please refer to Arm musca S1 [7]_ platform as a reference implementation when you enable FP support on your platforms. ============================ FP ABI type for SPE and NSPE ============================ FP design in Armv8.0-M [8]_ architecture requires consistent FP ABI types between SPE and NSPE. Furthermore, both sides shall set up CPACR individually when FPU is used. Otherwise, No Coprocessor (NOCP) usage fault will be asserted during FP context switch between security states. Secure and non-secure libraries are compiled with ``COMPILER_CP_FLAG`` and linked with ``LINKER_CP_OPTION`` for different FP ABI types. All those libraries shall be built with ``COMPLIER_CP_FLAG``. If FP ABI types mismatch error is generated during build, pleae check whether the library is compiled with ``COMPILER_CP_FLAG``. Example: .. code-block:: cmake target_compile_options(lib PRIVATE ${COMPILER_CP_FLAG} ) =================================== CMake configurations for FP support =================================== The following CMake configurations configure ``COMPILER_CP_FLAG`` in TF-M SPE. * ``CONFIG_TFM_FP`` are used to configure FP ABI type for secure and non-secure side both. +-------------------+---------------------------+ | CONFIG_TFM_FP | FP ABI type [2]_ [3]_ | +===================+===========================+ | soft (default) | Software | +-------------------+---------------------------+ | hard | Hardware | +-------------------+---------------------------+ FP software ABI type is default in TF-M. * ``CONFIG_TFM_LAZY_STACKING`` is used to enable/disable lazy stacking feature. This feature is only valid for FP hardware ABI type. NSPE is not allowed to enable/disable this feature. Let SPE decide the secure/non-secure shared setting of lazy stacking to avoid the possible side-path brought by flexibility. +------------------------------+---------------------------+ | CONFIG_TFM_LAZY_STACKING | Description | +==============================+===========================+ | 0FF | Disable lazy stacking | +------------------------------+---------------------------+ | ON (default) | Enable lazy stacking | +------------------------------+---------------------------+ * ``CONFIG_TFM_FP_ARCH`` specifies which FP architecture is available on the target, valid for FP hardware ABI type. FP architecture is processor dependent. For GNUARM compiler, example value are: auto, fpv5-d16, fpv5-sp-d16, etc. Default value of ``CONFIG_TFM_FP_ARCH`` for GNUARM compiler is fpv5-sp-d16. This parameter shall be specified by platform. Please check compiler reference manual and processor hardware manual for more details to set correct FPU configuration for platform. ********* Reference ********* .. [1] `High-Performance Hardware Support for Floating-Point Operations `_ .. [2] `Float Point ABI `_ .. [3] `GNU Arm Embedded Toolchain `_ .. [4] `VLLDM instruction Security Vulnerability `_ .. [5] `ArmĀ® Platform Security Architecture Firmware Framework 1.0 `_ .. [6] :doc:`Secure Interrupt Integration Guide ` .. [7] `Musca-S1 Test Chip Board `_ .. [8] `Armv8-M Architecture Reference Manual `_ -------------- *Copyright (c) 2021, Arm Limited. All rights reserved.*