xlnx,xps-uartlite-1.00.a

Vendor: Xilinx

Description

These nodes are “uart” bus nodes.

Xilinx UART Lite IP

Properties

Node specific properties

Base properties

Properties not inherited from the base binding file.

Name	Type	Details
clock-frequency	int	Clock frequency information for UART operation
current-speed	int	Initial baud rate setting for UART
hw-flow-control	boolean	Set to enable RTS/CTS flow control at boot time

Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “xlnx,xps-uartlite-1.00.a” compatible.

Name	Type	Details
reg	array	register space This property is required. See Important properties for more information.
label	string	Human readable string describing the device (used as device_get_binding() argument) This property is required. See Important properties for more information.
status	string	indicates the operational status of a device Legal values: 'ok', 'okay', 'disabled', 'reserved', 'fail', 'fail-sss' See Important properties for more information.
compatible	string-array	compatible strings This property is required. See Important properties for more information.
reg-names	string-array	name of each register space
interrupts	array	interrupts for device See Important properties for more information.
interrupts-extended	compound	extended interrupt specifier for device
interrupt-names	string-array	name of each interrupt
interrupt-parent	phandle	phandle to interrupt controller node
clocks	phandle-array	Clock gate information
clock-names	string-array	name of each clock
#address-cells	int	number of address cells in reg property
#size-cells	int	number of size cells in reg property
dmas	phandle-array	DMA channels specifiers
dma-names	string-array	Provided names of DMA channel specifiers
io-channels	phandle-array	IO channels specifiers
io-channel-names	string-array	Provided names of IO channel specifiers