xlnx,xps-timer-1.00.a-pwm¶
Vendor: Xilinx
Description¶
Xilinx AXI Timer IP node (PWM controller)
Properties¶
Properties not inherited from the base binding file.
Name |
Type |
Details |
---|---|---|
|
|
Active state of the generateout0 signal (0 for active-low, 1 for
active-high).
This property is required. Legal values: |
|
|
Active state of the generateout1 signal (0 for active-low, 1 for
active-high).
This property is required. Legal values: |
|
|
Active state of the capturetrig0 signal (0 for active-low, 1 for
active-high).
This property is required. Legal values: |
|
|
Active state of the capturetrig1 signal (0 for active-low, 1 for
active-high).
This property is required. Legal values: |
|
|
Clock frequency information for RTC operation
This property is required. |
|
|
Individual timer/counter width in bits.
This property is required. Legal values: |
|
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0 if both Timer 1 and Timer 2 are enabled, 1 if only Timer 1 is enabled.
This property is required. Legal values: |
|
|
RTC frequency equals clock-frequency divided by the prescaler value
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Number of items to expect in a pwm specifier
This property is required. |
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “xlnx,xps-timer-1.00.a-pwm” compatible.
Name |
Type |
Details |
---|---|---|
|
|
Human readable string describing the device (used as device_get_binding() argument)
This property is required. See Important properties for more information. |
|
|
interrupts for device
This property is required. See Important properties for more information. |
|
|
indicates the operational status of a device
Legal values: See Important properties for more information. |
|
|
compatible strings
This property is required. See Important properties for more information. |
|
|
register space
See Important properties for more information. |
|
|
name of each register space
|
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extended interrupt specifier for device
|
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name of each interrupt
|
|
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phandle to interrupt controller node
|
|
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Clock gate information
|
|
|
name of each clock
|
|
|
number of address cells in reg property
|
|
|
number of size cells in reg property
|
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DMA channels specifiers
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Provided names of DMA channel specifiers
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IO channels specifiers
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Provided names of IO channel specifiers
|
Specifier cell names¶
pwm cells: channel, period, flags