mikro-bus¶
Vendor: Generic or vendor-independent
Description¶
GPIO pins exposed on Mikro BUS headers.
The Mikro BUS layout provides two headers, aligned on the opposite
edges of the board.
Documentation:
* https://www.mikroe.com/mikrobus
* https://download.mikroe.com/documents/standards/mikrobus/mikrobus-standard-specification-v200.pdf
This binding provides a nexus mapping for 10 pins, left side pins are
numbered 0 - 5 (AN - MOSI), the right side pins are numbered 6 - 10
(PWM - SDA). The bottom 2 pins on each side are used for input voltage
and ground, they are not mapped in the nexus.
Analog - AN PWM - PWM output
Reset - RST INT - Hardware Interrupt
SPI Chip Select - CS RX - UART Receive
SPI Clock - SCK TX - UART Transmit
SPI Master Input Slave Output - MISO SCL - I2C Clock
SPI Master Output Slave Input - MOSI SDA - I2C Data
VCC-3.3V power - +3.3V +5V - VCC-5V power
Reference Ground - GND GND - Reference Ground
Board's silkscreen may vary depending you board, but coherent with
the description above as it's according to the standard's specification.
Properties¶
Properties not inherited from the base binding file.
Name |
Type |
Details |
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This property is required. |
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Number of items to expect in a GPIO specifier
This property is required. |
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “mikro-bus” compatible.
Name |
Type |
Details |
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indicates the operational status of a device
Legal values: See Important properties for more information. |
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compatible strings
This property is required. See Important properties for more information. |
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register space
See Important properties for more information. |
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name of each register space
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interrupts for device
See Important properties for more information. |
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extended interrupt specifier for device
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name of each interrupt
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phandle to interrupt controller node
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Human readable string describing the device (used as device_get_binding() argument)
See Important properties for more information. |
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Clock gate information
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name of each clock
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number of address cells in reg property
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number of size cells in reg property
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DMA channels specifiers
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Provided names of DMA channel specifiers
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IO channels specifiers
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Provided names of IO channel specifiers
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