Help¶

Use PLL2 as source of main PLL. This is equivalent of defining PLL2 as source PREDIV1SCR. If not selected, default source is HSE.

Direct dependencies¶

SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE && <choice: STM32 PLL Clock Source>

(Includes any dependencies from ifs and menus.)

Kconfig definition¶

At <Zephyr>/drivers/clock_control/Kconfig.stm32:112

Included via <Zephyr>/Kconfig:8 → <Zephyr>/Kconfig.zephyr:32 → <Zephyr>/drivers/Kconfig:54 → <Zephyr>/drivers/clock_control/Kconfig:25

Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control → STM32 PLL Clock Source

config CLOCK_STM32_PLL_SRC_PLL2
    bool "PLL2"
    depends on SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE && <choice: STM32 PLL Clock Source>
    help
      Use PLL2 as source of main PLL. This is equivalent of defining
      PLL2 as source PREDIV1SCR. If not selected, default source is HSE.

(The ‘depends on’ condition includes propagated dependencies from ifs and menus.)