CONFIG_CLOCK_STM32_PLL_R_DIVISOR

PLL R Divisor

PLL R Divisor

PLL R Divisor

PLL R Divisor

Type: int

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PLL R Output divisor, allowed values: 1-128.

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PLL R Output divisor, allowed values: 0, 2, 4, 6, 8.

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PLL R VCO divisor, allowed values: 2-8.

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PLL R Output divisor, allowed values: 2, 4, 6, 8.

Direct dependencies

(CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32H7X && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL) || (CLOCK_STM32_SYSCLK_SRC_PLL && (SOC_SERIES_STM32L4X || SOC_SERIES_STM32L5X || SOC_SERIES_STM32WBX) && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL) || (CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32G0X && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL) || (CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32G4X && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL)

(Includes any dependencies from ifs and menus.)

Defaults

• 2

• 4

• 2

• 2

Kconfig definitions

At <Zephyr>/drivers/clock_control/Kconfig.stm32h7:99

Included via <Zephyr>/Kconfig:8 → <Zephyr>/Kconfig.zephyr:32 → <Zephyr>/drivers/Kconfig:54 → <Zephyr>/drivers/clock_control/Kconfig:25 → <Zephyr>/drivers/clock_control/Kconfig.stm32:133

Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control

config CLOCK_STM32_PLL_R_DIVISOR
    int "PLL R Divisor"
    range 1 128
    default 2
    depends on CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32H7X && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL
    help
      PLL R Output divisor, allowed values: 1-128.

---

At <Zephyr>/drivers/clock_control/Kconfig.stm32l4_l5_wb:42

Included via <Zephyr>/Kconfig:8 → <Zephyr>/Kconfig.zephyr:32 → <Zephyr>/drivers/Kconfig:54 → <Zephyr>/drivers/clock_control/Kconfig:25 → <Zephyr>/drivers/clock_control/Kconfig.stm32:135

Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control

config CLOCK_STM32_PLL_R_DIVISOR
    int "PLL R Divisor"
    range 0 8
    default 4
    depends on CLOCK_STM32_SYSCLK_SRC_PLL && (SOC_SERIES_STM32L4X || SOC_SERIES_STM32L5X || SOC_SERIES_STM32WBX) && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL
    help
      PLL R Output divisor, allowed values: 0, 2, 4, 6, 8.

---

At <Zephyr>/drivers/clock_control/Kconfig.stm32g0:42

Included via <Zephyr>/Kconfig:8 → <Zephyr>/Kconfig.zephyr:32 → <Zephyr>/drivers/Kconfig:54 → <Zephyr>/drivers/clock_control/Kconfig:25 → <Zephyr>/drivers/clock_control/Kconfig.stm32:136

Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control

config CLOCK_STM32_PLL_R_DIVISOR
    int "PLL R Divisor"
    range 2 8
    default 2
    depends on CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32G0X && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL
    help
      PLL R VCO divisor, allowed values: 2-8.

---

At <Zephyr>/drivers/clock_control/Kconfig.stm32g4:40

Included via <Zephyr>/Kconfig:8 → <Zephyr>/Kconfig.zephyr:32 → <Zephyr>/drivers/Kconfig:54 → <Zephyr>/drivers/clock_control/Kconfig:25 → <Zephyr>/drivers/clock_control/Kconfig.stm32:137

Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control

config CLOCK_STM32_PLL_R_DIVISOR
    int "PLL R Divisor"
    range 2 8
    default 2
    depends on CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32G4X && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL
    help
      PLL R Output divisor, allowed values: 2, 4, 6, 8.

(The ‘depends on’ condition includes propagated dependencies from ifs and menus.)