-
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR
¶
Division factor for OTG FS, SDIO and RNG clocks
PLL Q Divisor
PLL Q Divisor
PLL Q Divisor
PLL Q Divisor
Type: int
Help¶
The USB OTG FS requires a 48MHz clock to work correctly. SDIO and RNG need a frequency lower than or equal to 48 MHz to work correctly. Allowed values: 2-15
Help¶
PLL Q Output divisor, allowed values: 1-128.
Help¶
PLL Q Output divisor, allowed values: 0, 2, 4, 6, 8.
Help¶
PLL Q VCO divisor, allowed values: 2-8. Limited to STM32G0X1 variants.
Help¶
PLL Q Output divisor, allowed values: 2, 4, 6, 8.
Direct dependencies¶
(CLOCK_STM32_SYSCLK_SRC_PLL
&& (SOC_SERIES_STM32F2X
|| SOC_SERIES_STM32F4X
|| SOC_SERIES_STM32F7X
) && CLOCK_CONTROL_STM32_CUBE
&& CLOCK_CONTROL
) || (CLOCK_STM32_SYSCLK_SRC_PLL
&& SOC_SERIES_STM32H7X
&& CLOCK_CONTROL_STM32_CUBE
&& CLOCK_CONTROL
) || (CLOCK_STM32_SYSCLK_SRC_PLL
&& (SOC_SERIES_STM32L4X
|| SOC_SERIES_STM32L5X
|| SOC_SERIES_STM32WBX
) && CLOCK_CONTROL_STM32_CUBE
&& CLOCK_CONTROL
) || (CLOCK_STM32_SYSCLK_SRC_PLL
&& (SOC_STM32G031XX
|| SOC_STM32G071XX
) && SOC_SERIES_STM32G0X
&& CLOCK_CONTROL_STM32_CUBE
&& CLOCK_CONTROL
) || (CLOCK_STM32_SYSCLK_SRC_PLL
&& SOC_SERIES_STM32G4X
&& CLOCK_CONTROL_STM32_CUBE
&& CLOCK_CONTROL
)
(Includes any dependencies from ifs and menus.)
Defaults¶
7
2
2
2
2
Kconfig definitions¶
At <Zephyr>/drivers/clock_control/Kconfig.stm32f2_f4_f7:40
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:32
→ <Zephyr>/drivers/Kconfig:54
→ <Zephyr>/drivers/clock_control/Kconfig:25
→ <Zephyr>/drivers/clock_control/Kconfig.stm32:132
Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control
config CLOCK_STM32_PLL_Q_DIVISOR int "Division factor for OTG FS, SDIO and RNG clocks" range 2 15 default 7 depends onCLOCK_STM32_SYSCLK_SRC_PLL
&& (SOC_SERIES_STM32F2X
||SOC_SERIES_STM32F4X
||SOC_SERIES_STM32F7X
) &&CLOCK_CONTROL_STM32_CUBE
&&CLOCK_CONTROL
help The USB OTG FS requires a 48MHz clock to work correctly. SDIO and RNG need a frequency lower than or equal to 48 MHz to work correctly. Allowed values: 2-15
At <Zephyr>/drivers/clock_control/Kconfig.stm32h7:91
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:32
→ <Zephyr>/drivers/Kconfig:54
→ <Zephyr>/drivers/clock_control/Kconfig:25
→ <Zephyr>/drivers/clock_control/Kconfig.stm32:133
Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control
config CLOCK_STM32_PLL_Q_DIVISOR int "PLL Q Divisor" range 1 128 default 2 depends onCLOCK_STM32_SYSCLK_SRC_PLL
&&SOC_SERIES_STM32H7X
&&CLOCK_CONTROL_STM32_CUBE
&&CLOCK_CONTROL
help PLL Q Output divisor, allowed values: 1-128.
At <Zephyr>/drivers/clock_control/Kconfig.stm32l4_l5_wb:34
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:32
→ <Zephyr>/drivers/Kconfig:54
→ <Zephyr>/drivers/clock_control/Kconfig:25
→ <Zephyr>/drivers/clock_control/Kconfig.stm32:135
Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control
config CLOCK_STM32_PLL_Q_DIVISOR int "PLL Q Divisor" range 0 8 default 2 depends onCLOCK_STM32_SYSCLK_SRC_PLL
&& (SOC_SERIES_STM32L4X
||SOC_SERIES_STM32L5X
||SOC_SERIES_STM32WBX
) &&CLOCK_CONTROL_STM32_CUBE
&&CLOCK_CONTROL
help PLL Q Output divisor, allowed values: 0, 2, 4, 6, 8.
At <Zephyr>/drivers/clock_control/Kconfig.stm32g0:33
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:32
→ <Zephyr>/drivers/Kconfig:54
→ <Zephyr>/drivers/clock_control/Kconfig:25
→ <Zephyr>/drivers/clock_control/Kconfig.stm32:136
Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control
config CLOCK_STM32_PLL_Q_DIVISOR int "PLL Q Divisor" range 2 8 default 2 depends onCLOCK_STM32_SYSCLK_SRC_PLL
&& (SOC_STM32G031XX
||SOC_STM32G071XX
) &&SOC_SERIES_STM32G0X
&&CLOCK_CONTROL_STM32_CUBE
&&CLOCK_CONTROL
help PLL Q VCO divisor, allowed values: 2-8. Limited to STM32G0X1 variants.
At <Zephyr>/drivers/clock_control/Kconfig.stm32g4:32
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:32
→ <Zephyr>/drivers/Kconfig:54
→ <Zephyr>/drivers/clock_control/Kconfig:25
→ <Zephyr>/drivers/clock_control/Kconfig.stm32:137
Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control
config CLOCK_STM32_PLL_Q_DIVISOR int "PLL Q Divisor" range 2 8 default 2 depends onCLOCK_STM32_SYSCLK_SRC_PLL
&&SOC_SERIES_STM32G4X
&&CLOCK_CONTROL_STM32_CUBE
&&CLOCK_CONTROL
help PLL Q Output divisor, allowed values: 2, 4, 6, 8.
(The ‘depends on’ condition includes propagated dependencies from ifs and menus.)