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CONFIG_CLOCK_STM32_PLL_P_DIVISOR
¶
PLL division factor for main system clock
PLL P Divisor
PLL P Divisor
PLL P Divisor
PLL P Divisor
Type: int
Help¶
PLLP division factor needs to be set correctly to not exceed 84MHz. Allowed values: 2, 4, 6, 8
Help¶
PLL P Output divisor, allowed values: 1-128.
Help¶
PLL P Output divisor, allowed values: 0, 7, 17.
Help¶
PLL P VCO divisor, allowed values: 2-32.
Help¶
PLL P Output divisor, allowed values: 7, 17.
Direct dependencies¶
(CLOCK_STM32_SYSCLK_SRC_PLL
&& (SOC_SERIES_STM32F2X
|| SOC_SERIES_STM32F4X
|| SOC_SERIES_STM32F7X
) && CLOCK_CONTROL_STM32_CUBE
&& CLOCK_CONTROL
) || (CLOCK_STM32_SYSCLK_SRC_PLL
&& SOC_SERIES_STM32H7X
&& CLOCK_CONTROL_STM32_CUBE
&& CLOCK_CONTROL
) || (CLOCK_STM32_SYSCLK_SRC_PLL
&& (SOC_SERIES_STM32L4X
|| SOC_SERIES_STM32L5X
|| SOC_SERIES_STM32WBX
) && CLOCK_CONTROL_STM32_CUBE
&& CLOCK_CONTROL
) || (CLOCK_STM32_SYSCLK_SRC_PLL
&& SOC_SERIES_STM32G0X
&& CLOCK_CONTROL_STM32_CUBE
&& CLOCK_CONTROL
) || (CLOCK_STM32_SYSCLK_SRC_PLL
&& SOC_SERIES_STM32G4X
&& CLOCK_CONTROL_STM32_CUBE
&& CLOCK_CONTROL
)
(Includes any dependencies from ifs and menus.)
Defaults¶
4
2
7
2
7
Kconfig definitions¶
At <Zephyr>/drivers/clock_control/Kconfig.stm32f2_f4_f7:31
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:32
→ <Zephyr>/drivers/Kconfig:54
→ <Zephyr>/drivers/clock_control/Kconfig:25
→ <Zephyr>/drivers/clock_control/Kconfig.stm32:132
Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control
config CLOCK_STM32_PLL_P_DIVISOR int "PLL division factor for main system clock" range 2 8 default 4 depends onCLOCK_STM32_SYSCLK_SRC_PLL
&& (SOC_SERIES_STM32F2X
||SOC_SERIES_STM32F4X
||SOC_SERIES_STM32F7X
) &&CLOCK_CONTROL_STM32_CUBE
&&CLOCK_CONTROL
help PLLP division factor needs to be set correctly to not exceed 84MHz. Allowed values: 2, 4, 6, 8
At <Zephyr>/drivers/clock_control/Kconfig.stm32h7:83
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:32
→ <Zephyr>/drivers/Kconfig:54
→ <Zephyr>/drivers/clock_control/Kconfig:25
→ <Zephyr>/drivers/clock_control/Kconfig.stm32:133
Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control
config CLOCK_STM32_PLL_P_DIVISOR int "PLL P Divisor" range 1 128 default 2 depends onCLOCK_STM32_SYSCLK_SRC_PLL
&&SOC_SERIES_STM32H7X
&&CLOCK_CONTROL_STM32_CUBE
&&CLOCK_CONTROL
help PLL P Output divisor, allowed values: 1-128.
At <Zephyr>/drivers/clock_control/Kconfig.stm32l4_l5_wb:26
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:32
→ <Zephyr>/drivers/Kconfig:54
→ <Zephyr>/drivers/clock_control/Kconfig:25
→ <Zephyr>/drivers/clock_control/Kconfig.stm32:135
Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control
config CLOCK_STM32_PLL_P_DIVISOR int "PLL P Divisor" range 0 17 default 7 depends onCLOCK_STM32_SYSCLK_SRC_PLL
&& (SOC_SERIES_STM32L4X
||SOC_SERIES_STM32L5X
||SOC_SERIES_STM32WBX
) &&CLOCK_CONTROL_STM32_CUBE
&&CLOCK_CONTROL
help PLL P Output divisor, allowed values: 0, 7, 17.
At <Zephyr>/drivers/clock_control/Kconfig.stm32g0:25
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:32
→ <Zephyr>/drivers/Kconfig:54
→ <Zephyr>/drivers/clock_control/Kconfig:25
→ <Zephyr>/drivers/clock_control/Kconfig.stm32:136
Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control
config CLOCK_STM32_PLL_P_DIVISOR int "PLL P Divisor" range 2 32 default 2 depends onCLOCK_STM32_SYSCLK_SRC_PLL
&&SOC_SERIES_STM32G0X
&&CLOCK_CONTROL_STM32_CUBE
&&CLOCK_CONTROL
help PLL P VCO divisor, allowed values: 2-32.
At <Zephyr>/drivers/clock_control/Kconfig.stm32g4:24
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:32
→ <Zephyr>/drivers/Kconfig:54
→ <Zephyr>/drivers/clock_control/Kconfig:25
→ <Zephyr>/drivers/clock_control/Kconfig.stm32:137
Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control
config CLOCK_STM32_PLL_P_DIVISOR int "PLL P Divisor" range 7 17 default 7 depends onCLOCK_STM32_SYSCLK_SRC_PLL
&&SOC_SERIES_STM32G4X
&&CLOCK_CONTROL_STM32_CUBE
&&CLOCK_CONTROL
help PLL P Output divisor, allowed values: 7, 17.
(The ‘depends on’ condition includes propagated dependencies from ifs and menus.)