Help¶

PREDIV is a PLL clock signal prescaler for the HSE output. It is supported by those parts that do not support PREDIV1. If configured on a non-supported part, this config will be ignored. Allowed values: 1 - 16.

Direct dependencies¶

CLOCK_STM32_SYSCLK_SRC_PLL && (SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X) && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL

(Includes any dependencies from ifs and menus.)

Default¶

1

Kconfig definition¶

At <Zephyr>/drivers/clock_control/Kconfig.stm32f0_f3:8

Included via <Zephyr>/Kconfig:8 → <Zephyr>/Kconfig.zephyr:32 → <Zephyr>/drivers/Kconfig:54 → <Zephyr>/drivers/clock_control/Kconfig:25 → <Zephyr>/drivers/clock_control/Kconfig.stm32:130

Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control

config CLOCK_STM32_PLL_PREDIV
    int "PREDIV Prescaler"
    range 1 16
    default 1
    depends on CLOCK_STM32_SYSCLK_SRC_PLL && (SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X) && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL
    help
      PREDIV is a PLL clock signal prescaler for the HSE output.
      It is supported by those parts that do not support PREDIV1.
      If configured on a non-supported part, this config will be ignored.
      Allowed values: 1 - 16.

(The ‘depends on’ condition includes propagated dependencies from ifs and menus.)