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CONFIG_CLOCK_STM32_PLL_M_DIVISOR
¶
Division factor for PLL VCO input clock
PLL divisor
PLL divisor
PLL divisor
PLL divisor
Type: int
Help¶
PLLM division factor needs to be set correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter. Allowed values: 2-63
Help¶
PLL divisor, allowed values: 0-63.
Help¶
PLL divisor, allowed values: 1-8. With this ensure that the PLL VCO input frequency ranges from 4 to 16MHz.
Help¶
PLL divisor, allowed values: 1-8.
Help¶
PLL divisor, allowed values: 1-16.
Direct dependencies¶
(CLOCK_STM32_SYSCLK_SRC_PLL
&& (SOC_SERIES_STM32F2X
|| SOC_SERIES_STM32F4X
|| SOC_SERIES_STM32F7X
) && CLOCK_CONTROL_STM32_CUBE
&& CLOCK_CONTROL
) || (CLOCK_STM32_SYSCLK_SRC_PLL
&& SOC_SERIES_STM32H7X
&& CLOCK_CONTROL_STM32_CUBE
&& CLOCK_CONTROL
) || (CLOCK_STM32_SYSCLK_SRC_PLL
&& (SOC_SERIES_STM32L4X
|| SOC_SERIES_STM32L5X
|| SOC_SERIES_STM32WBX
) && CLOCK_CONTROL_STM32_CUBE
&& CLOCK_CONTROL
) || (CLOCK_STM32_SYSCLK_SRC_PLL
&& SOC_SERIES_STM32G0X
&& CLOCK_CONTROL_STM32_CUBE
&& CLOCK_CONTROL
) || (CLOCK_STM32_SYSCLK_SRC_PLL
&& SOC_SERIES_STM32G4X
&& CLOCK_CONTROL_STM32_CUBE
&& CLOCK_CONTROL
)
(Includes any dependencies from ifs and menus.)
Defaults¶
8
32
1
1
4
Kconfig definitions¶
At <Zephyr>/drivers/clock_control/Kconfig.stm32f2_f4_f7:8
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:32
→ <Zephyr>/drivers/Kconfig:54
→ <Zephyr>/drivers/clock_control/Kconfig:25
→ <Zephyr>/drivers/clock_control/Kconfig.stm32:132
Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control
config CLOCK_STM32_PLL_M_DIVISOR int "Division factor for PLL VCO input clock" range 2 63 default 8 depends onCLOCK_STM32_SYSCLK_SRC_PLL
&& (SOC_SERIES_STM32F2X
||SOC_SERIES_STM32F4X
||SOC_SERIES_STM32F7X
) &&CLOCK_CONTROL_STM32_CUBE
&&CLOCK_CONTROL
help PLLM division factor needs to be set correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter. Allowed values: 2-63
At <Zephyr>/drivers/clock_control/Kconfig.stm32h7:67
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:32
→ <Zephyr>/drivers/Kconfig:54
→ <Zephyr>/drivers/clock_control/Kconfig:25
→ <Zephyr>/drivers/clock_control/Kconfig.stm32:133
Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control
config CLOCK_STM32_PLL_M_DIVISOR int "PLL divisor" range 0 63 default 32 depends onCLOCK_STM32_SYSCLK_SRC_PLL
&&SOC_SERIES_STM32H7X
&&CLOCK_CONTROL_STM32_CUBE
&&CLOCK_CONTROL
help PLL divisor, allowed values: 0-63.
At <Zephyr>/drivers/clock_control/Kconfig.stm32l4_l5_wb:8
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:32
→ <Zephyr>/drivers/Kconfig:54
→ <Zephyr>/drivers/clock_control/Kconfig:25
→ <Zephyr>/drivers/clock_control/Kconfig.stm32:135
Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control
config CLOCK_STM32_PLL_M_DIVISOR int "PLL divisor" range 1 8 default 1 depends onCLOCK_STM32_SYSCLK_SRC_PLL
&& (SOC_SERIES_STM32L4X
||SOC_SERIES_STM32L5X
||SOC_SERIES_STM32WBX
) &&CLOCK_CONTROL_STM32_CUBE
&&CLOCK_CONTROL
help PLL divisor, allowed values: 1-8. With this ensure that the PLL VCO input frequency ranges from 4 to 16MHz.
At <Zephyr>/drivers/clock_control/Kconfig.stm32g0:17
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:32
→ <Zephyr>/drivers/Kconfig:54
→ <Zephyr>/drivers/clock_control/Kconfig:25
→ <Zephyr>/drivers/clock_control/Kconfig.stm32:136
Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control
config CLOCK_STM32_PLL_M_DIVISOR int "PLL divisor" range 1 8 default 1 depends onCLOCK_STM32_SYSCLK_SRC_PLL
&&SOC_SERIES_STM32G0X
&&CLOCK_CONTROL_STM32_CUBE
&&CLOCK_CONTROL
help PLL divisor, allowed values: 1-8.
At <Zephyr>/drivers/clock_control/Kconfig.stm32g4:8
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:32
→ <Zephyr>/drivers/Kconfig:54
→ <Zephyr>/drivers/clock_control/Kconfig:25
→ <Zephyr>/drivers/clock_control/Kconfig.stm32:137
Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control
config CLOCK_STM32_PLL_M_DIVISOR int "PLL divisor" range 1 16 default 4 depends onCLOCK_STM32_SYSCLK_SRC_PLL
&&SOC_SERIES_STM32G4X
&&CLOCK_CONTROL_STM32_CUBE
&&CLOCK_CONTROL
help PLL divisor, allowed values: 1-16.
(The ‘depends on’ condition includes propagated dependencies from ifs and menus.)