Help¶

PLL multiplier, allowed values: 2-16. PLL output must not exceed 48MHz for STM32F0 series or 72MHz for STM32F3 series.

Help¶

PLL multiplier, PLL output must not exceed 72MHz. Allowed values: Density devices: 2-16 Connectivity devices: 4 - 9 and 13 ( used for multiplication factor 6.5).

Help¶

PLL multiplier, allowed values: 3, 4, 6, 8, 12, 16, 24, 32, 48. PLL output must not exceed 96MHz(1.8V)/48MHz(1.5V)/24MHz(1.2V).

Direct dependencies¶

(CLOCK_STM32_SYSCLK_SRC_PLL && (SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X) && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL) || (CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32F1X && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL) || (CLOCK_STM32_SYSCLK_SRC_PLL && (SOC_SERIES_STM32L0X || SOC_SERIES_STM32L1X) && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL)

(Includes any dependencies from ifs and menus.)

Defaults¶

6
9
4

Kconfig definitions¶

At <Zephyr>/drivers/clock_control/Kconfig.stm32f0_f3:31

Included via <Zephyr>/Kconfig:8 → <Zephyr>/Kconfig.zephyr:32 → <Zephyr>/drivers/Kconfig:54 → <Zephyr>/drivers/clock_control/Kconfig:25 → <Zephyr>/drivers/clock_control/Kconfig.stm32:130

Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control

config CLOCK_STM32_PLL_MULTIPLIER
    int "PLL multiplier"
    range 2 16
    default 6
    depends on CLOCK_STM32_SYSCLK_SRC_PLL && (SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X) && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL
    help
      PLL multiplier, allowed values: 2-16.
      PLL output must not exceed 48MHz for STM32F0 series
      or 72MHz for STM32F3 series.

At <Zephyr>/drivers/clock_control/Kconfig.stm32f1:8

Included via <Zephyr>/Kconfig:8 → <Zephyr>/Kconfig.zephyr:32 → <Zephyr>/drivers/Kconfig:54 → <Zephyr>/drivers/clock_control/Kconfig:25 → <Zephyr>/drivers/clock_control/Kconfig.stm32:131

Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control

config CLOCK_STM32_PLL_MULTIPLIER
    int "PLL multiplier"
    range 2 16 if SOC_STM32F10X_DENSITY_DEVICE
    range 4 9 if SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
    default 9
    depends on CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32F1X && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL
    help
      PLL multiplier, PLL output must not exceed 72MHz. Allowed values:
      Density devices: 2-16
      Connectivity devices:  4 - 9 and 13 ( used for multiplication factor 6.5).

At <Zephyr>/drivers/clock_control/Kconfig.stm32l0_l1:8

Included via <Zephyr>/Kconfig:8 → <Zephyr>/Kconfig.zephyr:32 → <Zephyr>/drivers/Kconfig:54 → <Zephyr>/drivers/clock_control/Kconfig:25 → <Zephyr>/drivers/clock_control/Kconfig.stm32:134

Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control

config CLOCK_STM32_PLL_MULTIPLIER
    int "PLL multiplier"
    range 3 48
    default 4
    depends on CLOCK_STM32_SYSCLK_SRC_PLL && (SOC_SERIES_STM32L0X || SOC_SERIES_STM32L1X) && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL
    help
      PLL multiplier, allowed values: 3, 4, 6, 8, 12, 16, 24, 32, 48.
      PLL output must not exceed 96MHz(1.8V)/48MHz(1.5V)/24MHz(1.2V).

(The ‘depends on’ condition includes propagated dependencies from ifs and menus.)