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CONFIG_CLOCK_STM32_PLL_DIVISOR
¶
PLL divisor
Type: int
Help¶
PLL divisor, allowed values: 2-4.
Direct dependencies¶
CLOCK_STM32_SYSCLK_SRC_PLL
&& (SOC_SERIES_STM32L0X
|| SOC_SERIES_STM32L1X
) && CLOCK_CONTROL_STM32_CUBE
&& CLOCK_CONTROL
(Includes any dependencies from ifs and menus.)
Default¶
2
Kconfig definition¶
At <Zephyr>/drivers/clock_control/Kconfig.stm32l0_l1:17
Included via <Zephyr>/Kconfig:8
→ <Zephyr>/Kconfig.zephyr:32
→ <Zephyr>/drivers/Kconfig:54
→ <Zephyr>/drivers/clock_control/Kconfig:25
→ <Zephyr>/drivers/clock_control/Kconfig.stm32:134
Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control
config CLOCK_STM32_PLL_DIVISOR int "PLL divisor" range 2 4 default 2 depends onCLOCK_STM32_SYSCLK_SRC_PLL
&& (SOC_SERIES_STM32L0X
||SOC_SERIES_STM32L1X
) &&CLOCK_CONTROL_STM32_CUBE
&&CLOCK_CONTROL
help PLL divisor, allowed values: 2-4.
(The ‘depends on’ condition includes propagated dependencies from ifs and menus.)