Driver Configuration Options

Kconfig files describe build-time configuration options (called symbols in Kconfig-speak), how they’re grouped into menus and sub-menus, and dependencies between them that determine what configurations are valid.

Kconfig files appear throughout the directory tree. For example, subsys/power/Kconfig defines power-related options.

This documentation is generated automatically from the Kconfig files by the genrest.py script. Click on symbols for more information.

Configuration Options

Symbol name

Help/prompt

CONFIG_2ND_LEVEL_INTERRUPTS

Second level interrupts are used to increase the number of addressable interrupts in a system.

CONFIG_2ND_LVL_INTR_00_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_2ND_LVL_INTR_01_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_2ND_LVL_INTR_02_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_2ND_LVL_INTR_03_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_2ND_LVL_INTR_04_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_2ND_LVL_INTR_05_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_2ND_LVL_INTR_06_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_2ND_LVL_INTR_07_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_2ND_LVL_ISR_TBL_OFFSET

This is the offset in _sw_isr_table, the generated ISR handler table, where storage for 2nd level interrupt ISRs begins. This is typically allocated after ISRs for level 1 interrupts.

CONFIG_3RD_LEVEL_INTERRUPTS

Third level interrupts are used to increase the number of addressable interrupts in a system.

CONFIG_3RD_LVL_INTR_00_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_3RD_LVL_INTR_01_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_3RD_LVL_INTR_02_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_3RD_LVL_INTR_03_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_3RD_LVL_INTR_04_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_3RD_LVL_INTR_05_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_3RD_LVL_INTR_06_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_3RD_LVL_INTR_07_OFFSET

This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator).

CONFIG_3RD_LVL_ISR_TBL_OFFSET

This is the offset in _sw_isr_table, the generated ISR handler table, where storage for 3rd level interrupt ISRs begins. This is typically allocated after ISRs for level 2 interrupts.

CONFIG_ADC

Enable ADC (Analog to Digital Converter) driver configuration.

CONFIG_ADC_0

Enable ADC 0

CONFIG_ADC_1

Enable ADC1

CONFIG_ADC_2

Enable ADC 2

CONFIG_ADC_ASYNC

This option enables the asynchronous API calls.

CONFIG_ADC_CONFIGURABLE_INPUTS

CONFIG_ADC_LMP90XXX

Enable LMP90xxx ADC driver.

The LMP90xxx is a multi-channel, low power sensor analog frontend (AFE).

CONFIG_ADC_LMP90XXX_ACQUISITION_THREAD_PRIO

Priority level for the internal ADC data acquisition thread.

CONFIG_ADC_LMP90XXX_ACQUISITION_THREAD_STACK_SIZE

Size of the stack used for the internal data acquisition thread.

CONFIG_ADC_LMP90XXX_CRC

Use Cyclic Redundancy Check (CRC) to verify the integrity of the data read from the LMP90xxx.

CONFIG_ADC_LMP90XXX_GPIO

Enable GPIO child device support in the LMP90xxx ADC driver.

The GPIO functionality is handled by the LMP90xxx GPIO driver.

CONFIG_ADC_LMP90XXX_INIT_PRIORITY

LMP90xxx ADC device driver initialization priority.

CONFIG_ADC_MCUX_ADC12

Enable the MCUX ADC12 driver.

CONFIG_ADC_MCUX_ADC16

Enable the MCUX ADC16 driver.

CONFIG_ADC_MCUX_ADC16_CLK_DIV_RATIO_1

Divide ratio is 1

CONFIG_ADC_MCUX_ADC16_CLK_DIV_RATIO_2

Divide ratio is 2

CONFIG_ADC_MCUX_ADC16_CLK_DIV_RATIO_4

Divide ratio is 4

CONFIG_ADC_MCUX_ADC16_CLK_DIV_RATIO_8

Divide ratio is 8

CONFIG_ADC_MCUX_ADC16_VREF_ALTERNATE

Alternate reference pair

CONFIG_ADC_MCUX_ADC16_VREF_DEFAULT

Default voltage reference pair V_REFH and V_REFL

CONFIG_ADC_NRFX_ADC

Enable support for nrfx ADC driver for nRF51 MCU series.

CONFIG_ADC_NRFX_ADC_CHANNEL_COUNT

Number of ADC channels to be supported by the driver. Each channel needs a dedicated structure in RAM that stores the ADC settings to be used when sampling this channel.

CONFIG_ADC_NRFX_SAADC

Enable support for nrfx SAADC driver for nRF52 MCU series.

CONFIG_ADC_SAM0

Enable Atmel SAM0 MCU Family Analog-to-Digital Converter (ADC) driver.

CONFIG_ADC_SAM_AFEC

Enable Atmel SAM MCU Family Analog-to-Digital Converter (ADC) driver based on AFEC module.

CONFIG_ADC_SHELL

Enable ADC Shell for testing.

CONFIG_ADC_STM32

Enable the driver implementation for the stm32xx ADC

CONFIG_ADC_XEC

Enable ADC driver for Microchip XEC MCU series.

CONFIG_ADT7420

Enable the driver for Analog Devices ADT7420 High-Accuracy 16-bit Digital I2C Temperature Sensors.

CONFIG_ADT7420_TEMP_CRIT

The critical overtemperature pin asserts when the temperature exceeds this value. The default value of 147 is the reset default of the ADT7420.

CONFIG_ADT7420_TEMP_HYST

Specify the temperature hysteresis in °C for the THIGH, TLOW, and TCRIT temperature limits.

CONFIG_ADT7420_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_ADT7420_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_ADT7420_TRIGGER

CONFIG_ADT7420_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_ADT7420_TRIGGER_NONE

No trigger

CONFIG_ADT7420_TRIGGER_OWN_THREAD

Use own thread

CONFIG_ADXL362

Enable driver for ADXL362 Three-Axis Digital Accelerometers.

CONFIG_ADXL362_ABS_REF_MODE

Unsigned value that sets the ADXL362 interrupt mode in either absolute or referenced mode. 0 - Absolute mode 1 - Referenced mode

CONFIG_ADXL362_ACCEL_ODR_100

100 Hz

CONFIG_ADXL362_ACCEL_ODR_12_5

12.5 Hz

CONFIG_ADXL362_ACCEL_ODR_200

200 Hz

CONFIG_ADXL362_ACCEL_ODR_25

25 Hz

CONFIG_ADXL362_ACCEL_ODR_400

400 Hz

CONFIG_ADXL362_ACCEL_ODR_50

50 Hz

CONFIG_ADXL362_ACCEL_ODR_RUNTIME

Set at runtime.

CONFIG_ADXL362_ACCEL_RANGE_2G

2G

CONFIG_ADXL362_ACCEL_RANGE_4G

4G

CONFIG_ADXL362_ACCEL_RANGE_8G

8G

CONFIG_ADXL362_ACCEL_RANGE_RUNTIME

Set at runtime.

CONFIG_ADXL362_ACTIVITY_THRESHOLD

Unsigned value that the adxl362 samples are compared to in activity trigger mode.

CONFIG_ADXL362_INACTIVITY_THRESHOLD

Unsigned value that the adxl362 samples are compared to in inactivity trigger mode.

CONFIG_ADXL362_INTERRUPT_MODE

Unsigned value that sets the ADXL362 in different interrupt modes. 0 - Default mode 1 - Linked mode 3 - Loop mode

CONFIG_ADXL362_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_ADXL362_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_ADXL362_TRIGGER

CONFIG_ADXL362_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_ADXL362_TRIGGER_NONE

No trigger

CONFIG_ADXL362_TRIGGER_OWN_THREAD

Use own thread

CONFIG_ADXL372

Enable driver for ADXL372 Three-Axis Digital Accelerometers.

CONFIG_ADXL372_ACTIVITY_THRESHOLD

Threshold for activity detection.

CONFIG_ADXL372_ACTIVITY_TIME

The activity timer implements a robust activity detection that minimizes false positive motion triggers. When the timer is used, only sustained motion can trigger activity detection. Number of multiples of 3.3 ms activity timer for which above threshold acceleration is required to detect activity. It is 3.3 ms per code for 6400 Hz ODR, and it is 6.6 ms per code for 3200 Hz ODR and below.

CONFIG_ADXL372_BW_1600HZ

1600 Hz

CONFIG_ADXL372_BW_200HZ

200 Hz

CONFIG_ADXL372_BW_3200HZ

3200 Hz

CONFIG_ADXL372_BW_400HZ

400 Hz

CONFIG_ADXL372_BW_800HZ

800 Hz

CONFIG_ADXL372_HPF_CORNER0

ODR/210

CONFIG_ADXL372_HPF_CORNER1

ODR/411

CONFIG_ADXL372_HPF_CORNER2

ODR/812

CONFIG_ADXL372_HPF_CORNER3

ODR/1616

CONFIG_ADXL372_HPF_DISABLE

Disabled

CONFIG_ADXL372_I2C

I2C Interface

CONFIG_ADXL372_INACTIVITY_THRESHOLD

Threshold for in-activity detection.

CONFIG_ADXL372_INACTIVITY_TIME

The time that all enabled axes must be lower than the inactivity threshold for an inactivity event to be detected. Number of multiples of 26 ms inactivity timer for which below threshold acceleration is required to detect inactivity. It is 26 ms per code for 3200 Hz ODR and below, and it is 13 ms per code for 6400 Hz ODR.

CONFIG_ADXL372_LPF_DISABLE

Disabled

CONFIG_ADXL372_MEASUREMENT_MODE

In this mode, acceleration data is provided continuously at the output data rate (ODR).

CONFIG_ADXL372_ODR_1600HZ

1600 Hz

CONFIG_ADXL372_ODR_3200HZ

3200 Hz

CONFIG_ADXL372_ODR_400HZ

400 Hz

CONFIG_ADXL372_ODR_6400HZ

6400 Hz

CONFIG_ADXL372_ODR_800HZ

800 Hz

CONFIG_ADXL372_PEAK_DETECT_MODE

In most high-g applications, a single (3-axis) acceleration sample at the peak of an impact event contains sufficient information about the event, and the full acceleration history is not required. In this mode the device returns only the over threshold Peak Acceleration between two consecutive sample fetches.

CONFIG_ADXL372_REFERENCED_ACTIVITY_DETECTION_MODE

Activity detection can be configured as referenced or absolute. When using absolute activity detection, acceleration samples are compared directly to a user set threshold to determine whether motion is present. In many applications, it is advantageous for activity detection to be based not on an absolute threshold, but on a deviation from a reference point or orientation.

CONFIG_ADXL372_SPI

SPI Interface

CONFIG_ADXL372_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_ADXL372_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_ADXL372_TRIGGER

CONFIG_ADXL372_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_ADXL372_TRIGGER_NONE

No trigger

CONFIG_ADXL372_TRIGGER_OWN_THREAD

Use own thread

CONFIG_AK8975

Enable driver for AK8975 magnetometer.

CONFIG_AK8975_I2C_ADDR

I2C address of the AK8975 sensor. Choose:

  • 0x0C if CAD1 connected to GND and CAD0 is connected to GND

  • 0x0D if CAD1 connected to GND and CAD0 is connected to VDD

  • 0x0E if CAD1 connected to VDD and CAD0 is connected to GND

  • 0x0F if CAD1 connected to VDD and CAD0 is connected to VDD

If the AK8975 sensor is part of a MPU9159 chip, the I2C address needs to be 0x0C.

CONFIG_AK8975_I2C_MASTER_DEV_NAME

Specify the device name of the I2C master device to which the AK8975 chip is connected.

CONFIG_AK8975_NAME

Device name with which the AK8975 sensor is identified.

CONFIG_ALTERA_AVALON_TIMER

This module implements a kernel device driver for the Altera Avalon Interval Timer as described in the Embedded IP documentation, for use with Nios II and possibly other Altera soft CPUs. It provides the standard “system clock driver” interfaces.

CONFIG_AMG88XX

Enable driver for AMG88XX infrared thermopile sensor.

CONFIG_AMG88XX_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_AMG88XX_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_AMG88XX_TRIGGER

CONFIG_AMG88XX_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_AMG88XX_TRIGGER_NONE

No trigger

CONFIG_AMG88XX_TRIGGER_OWN_THREAD

Use own thread

CONFIG_AMS_IAQ_CORE

Enable driver for iAQ-core Digital VOC sensor.

CONFIG_APA102_STRIP

Enable the LED strip driver for a chain of APA102 RGB LEDs. These are sold as DotStar by Adafruit and Superled by others.

CONFIG_APDS9960

Enable driver for APDS9960 sensors.

CONFIG_APDS9960_AGAIN_16X

16x

CONFIG_APDS9960_AGAIN_1X

1x

CONFIG_APDS9960_AGAIN_4X

4x

CONFIG_APDS9960_AGAIN_64X

64x

CONFIG_APDS9960_ENABLE_ALS

Enable Ambient Light Sense (ALS).

CONFIG_APDS9960_PGAIN_1X

1x

CONFIG_APDS9960_PGAIN_2X

2x

CONFIG_APDS9960_PGAIN_4X

4x

CONFIG_APDS9960_PGAIN_8X

8x

CONFIG_APDS9960_PLED_BOOST_100PCT

100%

CONFIG_APDS9960_PLED_BOOST_150PCT

150%

CONFIG_APDS9960_PLED_BOOST_200PCT

200%

CONFIG_APDS9960_PLED_BOOST_300PCT

300%

CONFIG_APDS9960_PPULSE_COUNT

Proximity Pulse Count

CONFIG_APDS9960_PPULSE_LENGTH_16US

16us

CONFIG_APDS9960_PPULSE_LENGTH_32US

32us

CONFIG_APDS9960_PPULSE_LENGTH_4US

4us

CONFIG_APDS9960_PPULSE_LENGTH_8US

8us

CONFIG_APDS9960_TRIGGER

CONFIG_APDS9960_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_APDS9960_TRIGGER_NONE

No trigger

CONFIG_APIC_TIMER

Use the “new” local APIC timer driver for the system timer. This is a replacement for the legacy local APIC timer driver which supports tickless operation, but not the Quark MVIC.

CONFIG_APIC_TIMER_IRQ

This option specifies the IRQ used by the local APIC timer.

CONFIG_APIC_TIMER_IRQ_PRIORITY

This option specifies the IRQ priority used by the local APIC timer.

CONFIG_APIC_TIMER_TSC

If your CPU supports invariant TSC, and you know the ratio of the TSC frequency to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC (the local APIC timer frequency), then enable this for a much faster and more accurate z_timer_cycle_get_32().

CONFIG_APIC_TIMER_TSC_M

TSC to local APIC timer frequency divisor (M)

CONFIG_APIC_TIMER_TSC_N

TSC to local APIC timer frequency multiplier (N)

CONFIG_ARCV2_INTERRUPT_UNIT

The ARCv2 interrupt unit has 16 allocated exceptions associated with vectors 0 to 15 and 240 interrupts associated with vectors 16 to 255. The interrupt unit is optional in the ARCv2-based processors. When building a processor, you can configure the processor to include an interrupt unit. The ARCv2 interrupt unit is highly programmable.

CONFIG_ARCV2_TIMER

This module implements a kernel device driver for the ARCv2 processor timer 0 and provides the standard “system clock driver” interfaces.

CONFIG_ARCV2_TIMER_IRQ_PRIORITY

This option specifies the IRQ priority used by the ARC timer. Lower values have higher priority.

CONFIG_ARM_CLOCK_CONTROL_DEV_NAME

Configure Clock Config Device name

CONFIG_AUDIO

Enable support for Audio

CONFIG_AUDIO_CODEC

Enable Audio Codec Driver Configuration

CONFIG_AUDIO_CODEC_INIT_PRIORITY

Audio codec device driver initialization priority.

CONFIG_AUDIO_DMIC

Enable Digital Microphone Driver Configuration

CONFIG_AUDIO_DMIC_INIT_PRIORITY

Audio Digital Microphone device driver initialization priority.

CONFIG_AUDIO_INTEL_DMIC

Enable Intel digital PDM microphone driver

CONFIG_AUDIO_MPXXDTYY

Enable MPXXDTYY microphone support on the selected board

CONFIG_AUDIO_TLV320DAC

Enable TLV320DAC support on the selected board

CONFIG_BMA280

Enable driver for BMA280 I2C-based triaxial accelerometer sensor family.

CONFIG_BMA280_PMU_BW_1

7.81Hz

CONFIG_BMA280_PMU_BW_2

15.63HZ

CONFIG_BMA280_PMU_BW_3

31.25Hz

CONFIG_BMA280_PMU_BW_4

62.5Hz

CONFIG_BMA280_PMU_BW_5

125Hz

CONFIG_BMA280_PMU_BW_6

250HZ

CONFIG_BMA280_PMU_BW_7

500Hz

CONFIG_BMA280_PMU_BW_8

unfiltered

CONFIG_BMA280_PMU_RANGE_16G

+/-16g

CONFIG_BMA280_PMU_RANGE_2G

+/-2g

CONFIG_BMA280_PMU_RANGE_4G

+/-4g

CONFIG_BMA280_PMU_RANGE_8G

+/-8g

CONFIG_BMA280_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_BMA280_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_BMA280_TRIGGER

CONFIG_BMA280_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_BMA280_TRIGGER_NONE

No trigger

CONFIG_BMA280_TRIGGER_OWN_THREAD

Use own thread

CONFIG_BMC150_MAGN

Enable driver for BMC150 I2C-based magnetometer sensor.

CONFIG_BMC150_MAGN_PRESET_ENHANCED_REGULAR

Enhanced regular (15, 27, 10)

CONFIG_BMC150_MAGN_PRESET_HIGH_ACCURACY

High accuracy (47, 83, 20)

CONFIG_BMC150_MAGN_PRESET_LOW_POWER

Low power (3, 3, 10)

CONFIG_BMC150_MAGN_PRESET_REGULAR

Regular (9, 15, 10)

CONFIG_BMC150_MAGN_SAMPLING_RATE_RUNTIME

Enable alteration of sampling rate attribute at runtime.

CONFIG_BMC150_MAGN_SAMPLING_REP_XY

Enable alteration of XY oversampling at runtime.

CONFIG_BMC150_MAGN_SAMPLING_REP_Z

Enable alteration of Z oversampling at runtime.

CONFIG_BMC150_MAGN_TRIGGER

Enable triggers for BMC150 magnetometer

CONFIG_BMC150_MAGN_TRIGGER_DRDY

Enable data ready interrupt for BMC150 magnetometer

CONFIG_BMC150_MAGN_TRIGGER_THREAD_STACK

Specify the internal thread stack size.

CONFIG_BME280

Enable driver for BME280 I2C-based or SPI-based temperature and pressure sensor.

CONFIG_BME280_FILTER_16

16

CONFIG_BME280_FILTER_2

2

CONFIG_BME280_FILTER_4

4

CONFIG_BME280_FILTER_8

8

CONFIG_BME280_FILTER_OFF

filter off

CONFIG_BME280_HUMIDITY_OVER_16X

x16

CONFIG_BME280_HUMIDITY_OVER_1X

x1

CONFIG_BME280_HUMIDITY_OVER_2X

x2

CONFIG_BME280_HUMIDITY_OVER_4X

x4

CONFIG_BME280_HUMIDITY_OVER_8X

x8

CONFIG_BME280_PRESS_OVER_16X

x16

CONFIG_BME280_PRESS_OVER_1X

x1

CONFIG_BME280_PRESS_OVER_2X

x2

CONFIG_BME280_PRESS_OVER_4X

x4

CONFIG_BME280_PRESS_OVER_8X

x8

CONFIG_BME280_STANDBY_05MS

0.5ms

CONFIG_BME280_STANDBY_1000MS

1000ms

CONFIG_BME280_STANDBY_125MS

125ms

CONFIG_BME280_STANDBY_2000MS

2000ms BMP280 / 10ms BME280

CONFIG_BME280_STANDBY_250MS

250ms

CONFIG_BME280_STANDBY_4000MS

4000ms BMP280 / 20ms BME280

CONFIG_BME280_STANDBY_500MS

500ms

CONFIG_BME280_STANDBY_62MS

62.5ms

CONFIG_BME280_TEMP_OVER_16X

x16

CONFIG_BME280_TEMP_OVER_1X

x1

CONFIG_BME280_TEMP_OVER_2X

x2

CONFIG_BME280_TEMP_OVER_4X

x4

CONFIG_BME280_TEMP_OVER_8X

x8

CONFIG_BME680

Enable driver for BME680 I2C-based based temperature, pressure, humidity and gas sensor.

CONFIG_BME680_FILTER_128

128

CONFIG_BME680_FILTER_16

16

CONFIG_BME680_FILTER_2

2

CONFIG_BME680_FILTER_32

32

CONFIG_BME680_FILTER_4

4

CONFIG_BME680_FILTER_64

64

CONFIG_BME680_FILTER_8

8

CONFIG_BME680_FILTER_OFF

filter off

CONFIG_BME680_HEATR_DUR_LP

197

CONFIG_BME680_HEATR_DUR_ULP

1943

CONFIG_BME680_HEATR_TEMP_LP

320

CONFIG_BME680_HEATR_TEMP_ULP

400

CONFIG_BME680_HUMIDITY_OVER_16X

x16

CONFIG_BME680_HUMIDITY_OVER_1X

x1

CONFIG_BME680_HUMIDITY_OVER_2X

x2

CONFIG_BME680_HUMIDITY_OVER_4X

x4

CONFIG_BME680_HUMIDITY_OVER_8X

x8

CONFIG_BME680_PRESS_OVER_16X

x16

CONFIG_BME680_PRESS_OVER_1X

x1

CONFIG_BME680_PRESS_OVER_2X

x2

CONFIG_BME680_PRESS_OVER_4X

x4

CONFIG_BME680_PRESS_OVER_8X

x8

CONFIG_BME680_TEMP_OVER_16X

x16

CONFIG_BME680_TEMP_OVER_1X

x1

CONFIG_BME680_TEMP_OVER_2X

x2

CONFIG_BME680_TEMP_OVER_4X

x4

CONFIG_BME680_TEMP_OVER_8X

x8

CONFIG_BMG160

Enable Bosch BMG160 gyroscope support.

CONFIG_BMG160_I2C_SPEED_FAST

Fast bus speed of up to 400KHz.

CONFIG_BMG160_I2C_SPEED_STANDARD

Standard bus speed of up to 100kHz.

CONFIG_BMG160_ODR_100

100 Hz

CONFIG_BMG160_ODR_1000

1000 Hz

CONFIG_BMG160_ODR_200

200 Hz

CONFIG_BMG160_ODR_2000

2000 Hz

CONFIG_BMG160_ODR_400

400 Hz

CONFIG_BMG160_ODR_RUNTIME

Set at runtime.

CONFIG_BMG160_RANGE_1000DPS

1000 DPS

CONFIG_BMG160_RANGE_125DPS

125 DPS

CONFIG_BMG160_RANGE_2000DPS

2000 DPS

CONFIG_BMG160_RANGE_250DPS

250 DPS

CONFIG_BMG160_RANGE_500DPS

500 DPS

CONFIG_BMG160_RANGE_RUNTIME

Set at runtime.

CONFIG_BMG160_THREAD_PRIORITY

The priority of the thread used for handling interrupts.

CONFIG_BMG160_THREAD_STACK_SIZE

The thread stack size.

CONFIG_BMG160_TRIGGER

CONFIG_BMG160_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_BMG160_TRIGGER_NONE

No trigger

CONFIG_BMG160_TRIGGER_OWN_THREAD

Use own thread

CONFIG_BMI160

Enable Bosch BMI160 inertial measurement unit that provides acceleration and angular rate measurements.

CONFIG_BMI160_ACCEL_ODR_100

100 Hz

CONFIG_BMI160_ACCEL_ODR_1600

1600 Hz

CONFIG_BMI160_ACCEL_ODR_200

200 Hz

CONFIG_BMI160_ACCEL_ODR_25

25 Hz

CONFIG_BMI160_ACCEL_ODR_25_16

1.56 Hz

CONFIG_BMI160_ACCEL_ODR_25_2

12.5 Hz

CONFIG_BMI160_ACCEL_ODR_25_32

0.78 Hz

CONFIG_BMI160_ACCEL_ODR_25_4

6.25 Hz

CONFIG_BMI160_ACCEL_ODR_25_8

3.125 Hz

CONFIG_BMI160_ACCEL_ODR_400

400 Hz

CONFIG_BMI160_ACCEL_ODR_50

50 Hz

CONFIG_BMI160_ACCEL_ODR_800

800 Hz

CONFIG_BMI160_ACCEL_ODR_RUNTIME

Set at runtime.

CONFIG_BMI160_ACCEL_PMU_LOW_POWER

low power

CONFIG_BMI160_ACCEL_PMU_NORMAL

normal

CONFIG_BMI160_ACCEL_PMU_RUNTIME

Set at runtime.

CONFIG_BMI160_ACCEL_PMU_SUSPEND

suspended/not used

CONFIG_BMI160_ACCEL_RANGE_16G

16G

CONFIG_BMI160_ACCEL_RANGE_2G

2G

CONFIG_BMI160_ACCEL_RANGE_4G

4G

CONFIG_BMI160_ACCEL_RANGE_8G

8G

CONFIG_BMI160_ACCEL_RANGE_RUNTIME

Set at runtime.

CONFIG_BMI160_GYRO_ODR_100

100 Hz

CONFIG_BMI160_GYRO_ODR_1600

1600 Hz

CONFIG_BMI160_GYRO_ODR_200

200 Hz

CONFIG_BMI160_GYRO_ODR_25

25 Hz

CONFIG_BMI160_GYRO_ODR_3200

3200 Hz

CONFIG_BMI160_GYRO_ODR_400

400 Hz

CONFIG_BMI160_GYRO_ODR_50

50 Hz

CONFIG_BMI160_GYRO_ODR_800

800 Hz

CONFIG_BMI160_GYRO_ODR_RUNTIME

Set at runtime.

CONFIG_BMI160_GYRO_PMU_FAST_STARTUP

fast start-up

CONFIG_BMI160_GYRO_PMU_NORMAL

normal

CONFIG_BMI160_GYRO_PMU_RUNTIME

Set at runtime.

CONFIG_BMI160_GYRO_PMU_SUSPEND

suspended/not used

CONFIG_BMI160_GYRO_RANGE_1000DPS

1000 DPS

CONFIG_BMI160_GYRO_RANGE_125DPS

125 DPS

CONFIG_BMI160_GYRO_RANGE_2000DPS

2000 DPS

CONFIG_BMI160_GYRO_RANGE_250DPS

250 DPS

CONFIG_BMI160_GYRO_RANGE_500DPS

500 DPS

CONFIG_BMI160_GYRO_RANGE_RUNTIME

Set at runtime.

CONFIG_BMI160_THREAD_PRIORITY

The priority of the thread used for handling interrupts.

CONFIG_BMI160_THREAD_STACK_SIZE

The thread stack size.

CONFIG_BMI160_TRIGGER

CONFIG_BMI160_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_BMI160_TRIGGER_NONE

No trigger

CONFIG_BMI160_TRIGGER_OWN_THREAD

Use own thread

CONFIG_BMM150

Enable driver for BMM150 I2C-based Geomagnetic sensor.

CONFIG_BMM150_PRESET_ENHANCED_REGULAR

Enhanced regular (15, 27, 10)

CONFIG_BMM150_PRESET_HIGH_ACCURACY

High accuracy (47, 83, 20)

CONFIG_BMM150_PRESET_LOW_POWER

Low power (3, 3, 10)

CONFIG_BMM150_PRESET_REGULAR

Regular (9, 15, 10)

CONFIG_BMM150_SAMPLING_RATE_RUNTIME

Enable alteration of sampling rate attribute at runtime.

CONFIG_BMM150_SAMPLING_REP_XY

Enable alteration of XY oversampling at runtime.

CONFIG_BMM150_SAMPLING_REP_Z

Enable alteration of Z oversampling at runtime.

CONFIG_BT_BLUENRG_ACI

Enable support for devices compatible with the BlueNRG Bluetooth Stack. Current driver supports: ST BLUENRG-MS.

CONFIG_BT_H4

Bluetooth H:4 UART driver. Requires hardware flow control lines to be available.

CONFIG_BT_H5

Bluetooth three-wire (H:5) UART driver. Implementation of HCI Three-Wire UART Transport Layer.

CONFIG_BT_NO_DRIVER

This is intended for unit tests where no internal driver should be selected.

CONFIG_BT_RPMSG

Bluetooth HCI driver for communication with another CPU using RPMsg framework.

CONFIG_BT_RPMSG_NRF53

Enable RPMsg configuration for nRF53. Two channels of the IPM driver are used in the HCI driver: channel 0 for TX and channel 1 for RX.

CONFIG_BT_RPMSG_NRF53_RX_PRIO

RPMsg RX thread priority

CONFIG_BT_RPMSG_NRF53_RX_STACK_SIZE

RPMsg stack size for RX thread

CONFIG_BT_SPI

Supports Bluetooth ICs using SPI as the communication protocol. HCI packets are sent and received as single Byte transfers, prepended after a known header. Headers may vary per device, so additional platform specific knowledge may need to be added as devices are.

CONFIG_BT_SPI_BLUENRG

Enable support for devices compatible with the BlueNRG Bluetooth Stack. Current driver supports: ST BLUENRG-MS.

CONFIG_BT_STM32_IPM

TODO

CONFIG_BT_UART

CONFIG_BT_UART_ON_DEV_NAME

This option specifies the name of UART device to be used for Bluetooth.

CONFIG_BT_USERCHAN

This driver provides access to the local Linux host’s Bluetooth adapter using a User Channel HCI socket to the Linux kernel. It is only intended to be used with the native POSIX build of Zephyr. The Bluetooth adapter must be powered off in order for Zephyr to be able to use it.

CONFIG_CAN

Enable CAN Driver Configuration

CONFIG_CAN_0

Enable CAN controller 0

CONFIG_CAN_1

Enable CAN controller 1

CONFIG_CAN_AUTO_BUS_OFF_RECOVERY

This option enables the automatic bus-off recovery according to ISO 11898-1 (recovery after 128 occurrences of 11 consecutive recessive bits). When this option is enabled, the recovery API is not available.

CONFIG_CAN_INIT_PRIORITY

CAN device driver initialization priority. Do not mess with it unless you know what you are doing. Note that the priority needs to be lower than the net stack so that it can start before the networking sub-system.

CONFIG_CAN_LOOPBACK

This is a dummy driver that can only loopback messages.

CONFIG_CAN_LOOPBACK_DEV_NAME

“Device name for the loopback device”

CONFIG_CAN_MAX_FILTER

Defines the array size of the callback/msgq pointers. Must be at least the size of concurrent reads.

CONFIG_CAN_MCP2515

Enable MCP2515 CAN Driver

CONFIG_CAN_MCP2515_INIT_PRIORITY

MCP2515 driver initialization priority, must be higher than SPI.

CONFIG_CAN_MCP2515_INT_THREAD_PRIO

Priority level of the internal thread which is ran for interrupt handling and incoming packets.

CONFIG_CAN_MCP2515_INT_THREAD_STACK_SIZE

Size of the stack used for internal thread which is ran for interrupt handling and incoming packets.

CONFIG_CAN_MCP2515_MAX_FILTER

Defines the array size of the callback/msgq pointers. Must be at least the size of concurrent reads.

CONFIG_CAN_MCUX_FLEXCAN

Enable support for mcux flexcan driver.

CONFIG_CAN_NET

Enable IPv6 Networking over can (6loCAN)

CONFIG_CAN_NET_INIT_PRIORITY

CAN NET device driver initialization priority. Do not mess with it unless you know what you are doing. Note that the priority needs to be lower than the net stack so that it can start before the networking sub-system.

CONFIG_CAN_NET_NAME

Name of the network device driver for IPv6 over CAN.

CONFIG_CAN_RX_TIMESTAMP

This option enables a timestamp value of the CAN free running timer. The value is incremented every bit time and starts when the controller is initialized.

CONFIG_CAN_SHELL

Enable CAN Shell for testing.

CONFIG_CAN_STM32

Enable STM32 CAN Driver. Tested on stm32F0, stm32L4 and stm32F7 series.

CONFIG_CAN_WORKQ_FRAMES_BUF_CNT

Number of frames in the buffer of a zcan_work.

CONFIG_CAVS_ICTL

These are 4 in number supporting a max of 32 interrupts each.

CONFIG_CAVS_ICTL_0_NAME

CAVS 0 Driver name

CONFIG_CAVS_ICTL_0_OFFSET

Parent interrupt number to which CAVS_0 maps

CONFIG_CAVS_ICTL_1_NAME

CAVS 1 Driver name

CONFIG_CAVS_ICTL_1_OFFSET

Parent interrupt number to which CAVS_1 maps

CONFIG_CAVS_ICTL_2_NAME

CAVS 2 Driver name

CONFIG_CAVS_ICTL_2_OFFSET

Parent interrupt number to which CAVS_2 maps

CONFIG_CAVS_ICTL_3_NAME

CAVS 3 Driver name

CONFIG_CAVS_ICTL_3_OFFSET

Parent interrupt number to which CAVS_3 maps

CONFIG_CAVS_ICTL_INIT_PRIORITY

Cavs Interrupt Logic initialization priority.

CONFIG_CAVS_ISR_TBL_OFFSET

This indicates the offset in the SW_ISR_TABLE beginning from where the ISRs for CAVS Interrupt Controller are assigned.

CONFIG_CC13X2_CC26X2_RTC_TIMER

This module implements a kernel device driver for the TI SimpleLink CC13X2_CC26X2 series Real Time Counter and provides the standard “system clock driver” interfaces.

CONFIG_CCS811

Enable driver for CCS811 Gas sensors.

CONFIG_CCS811_DRIVE_MODE_0

Measurements disabled

CONFIG_CCS811_DRIVE_MODE_1

Measurement every second

CONFIG_CCS811_DRIVE_MODE_2

Measurement every ten seconds

CONFIG_CCS811_DRIVE_MODE_3

Measurement every sixty seconds

CONFIG_CCS811_DRIVE_MODE_4

Measurement every 250 milliseconds

CONFIG_CCS811_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_CCS811_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_CCS811_TRIGGER

CONFIG_CCS811_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_CCS811_TRIGGER_NONE

No trigger

CONFIG_CCS811_TRIGGER_OWN_THREAD

Use own thread

CONFIG_CLOCK_CONTROL

Enable support for hardware clock controller. Such hardware can provide clock for other subsystem, and thus can be also used for power efficiency by controlling their clock. Note that this has nothing to do with RTC.

CONFIG_CLOCK_CONTROL_BEETLE

Enable driver for Reset & Clock Control subsystem found in STM32F4 family of MCUs

CONFIG_CLOCK_CONTROL_BEETLE_DEVICE_INIT_PRIORITY

This option controls the priority of clock control device initialization. Higher priority ensures that the device is initialized earlier in the startup cycle. If unsure, leave at default value 1

CONFIG_CLOCK_CONTROL_BEETLE_ENABLE_PLL

Enable PLL on Beetle.

Select n if not sure.

CONFIG_CLOCK_CONTROL_MCUX_CCM

Enable support for mcux ccm driver.

CONFIG_CLOCK_CONTROL_MCUX_MCG

Enable support for mcux mcg driver.

CONFIG_CLOCK_CONTROL_MCUX_PCC

Enable support for MCUX PCC driver.

CONFIG_CLOCK_CONTROL_MCUX_SCG

Enable support for mcux scg driver.

CONFIG_CLOCK_CONTROL_MCUX_SIM

Enable support for mcux sim driver.

CONFIG_CLOCK_CONTROL_NRF

Enable support for the Nordic Semiconductor nRFxx series SoC clock driver.

CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_DEBUG

Enables retrieving debug information like number of performed or skipped calibrations.

CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_MAX_SKIP

Calibration is skipped when temperature change since last calibration was less than configured threshold. If number of consecutive skips reaches configured value then calibration is performed unconditionally. Set to 0 to perform calibration periodically regardless of temperature change.

CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD

Periodically, calibration action is performed. Action includes temperature measurement followed by clock calibration. Calibration may be skipped if temperature change (compared to measurement of previous calibration) did not exceeded CLOCK_CONTROL_NRF_CALIBRATION_TEMP_DIFF and number of consecutive skips did not exceeded CLOCK_CONTROL_NRF_CALIBRATION_MAX_SKIP.

CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_TEMP_DIFF

Calibration is triggered if the temperature has changed by at least this amount since the last calibration.

CONFIG_CLOCK_CONTROL_NRF_FORCE_ALT

This option can be enabled to force an alternative implementation of the clock control driver.

CONFIG_CLOCK_CONTROL_NRF_K32SRC_100PPM

76 ppm to 100 ppm

CONFIG_CLOCK_CONTROL_NRF_K32SRC_150PPM

101 ppm to 150 ppm

CONFIG_CLOCK_CONTROL_NRF_K32SRC_20PPM

0 ppm to 20 ppm

CONFIG_CLOCK_CONTROL_NRF_K32SRC_250PPM

151 ppm to 250 ppm

CONFIG_CLOCK_CONTROL_NRF_K32SRC_30PPM

21 ppm to 30 ppm

CONFIG_CLOCK_CONTROL_NRF_K32SRC_500PPM

251 ppm to 500 ppm

CONFIG_CLOCK_CONTROL_NRF_K32SRC_50PPM

31 ppm to 50 ppm

CONFIG_CLOCK_CONTROL_NRF_K32SRC_75PPM

51 ppm to 75 ppm

CONFIG_CLOCK_CONTROL_NRF_K32SRC_EXT_FULL_SWING

External full swing

CONFIG_CLOCK_CONTROL_NRF_K32SRC_EXT_LOW_SWING

External low swing

CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC

RC Oscillator

CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC_CALIBRATION

CONFIG_CLOCK_CONTROL_NRF_K32SRC_SYNTH

Synthesized from HFCLK

CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL

Crystal Oscillator

CONFIG_CLOCK_CONTROL_NRF_USES_TEMP_SENSOR

CONFIG_CLOCK_CONTROL_RV32M1_PCC

Enable support for RV32M1 PCC driver.

CONFIG_CLOCK_CONTROL_STM32_CUBE

Enable driver for Reset & Clock Control subsystem found in STM32 family of MCUs

CONFIG_CLOCK_CONTROL_STM32_DEVICE_INIT_PRIORITY

This option controls the priority of clock control device initialization. Higher priority ensures that the device is initialized earlier in the startup cycle. If unsure, leave at default value 1

CONFIG_CLOCK_STM32_AHB4_PRESCALER

HCLK4 prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512.

CONFIG_CLOCK_STM32_AHB_PRESCALER

AHB prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512.

CONFIG_CLOCK_STM32_APB1_PRESCALER

APB1 Low speed clock (PCLK1) prescaler, allowed values: 1, 2, 4, 8, 16

CONFIG_CLOCK_STM32_APB2_PRESCALER

APB2 High speed clock (PCLK2) prescaler, allowed values: 1, 2, 4, 8, 16

CONFIG_CLOCK_STM32_CPU1_PRESCALER

CPU1 HCLK prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512.

CONFIG_CLOCK_STM32_CPU2_PRESCALER

CPU2 HCLK prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512.

CONFIG_CLOCK_STM32_D1CPRE

D1 Domain, CPU1 clock (sys_d1cpre_ck prescaler), allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512.

CONFIG_CLOCK_STM32_D1PPRE

APB3 clock (rcc_pclk3) prescaler, allowed values: 1, 2, 4, 8, 16

CONFIG_CLOCK_STM32_D2PPRE1

APB1 clock (rcc_pclk1) prescaler, allowed values: 1, 2, 4, 8, 16

CONFIG_CLOCK_STM32_D2PPRE2

APB2 clock (rcc_pclk2) prescaler, allowed values: 1, 2, 4, 8, 16

CONFIG_CLOCK_STM32_D3PPRE

APB4 clock (rcc_pclk4) prescaler, allowed values: 1, 2, 4, 8, 16

CONFIG_CLOCK_STM32_HPRE

hclk prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512.

CONFIG_CLOCK_STM32_HSE_BYPASS

Enable this option to bypass external high-speed clock (HSE).

CONFIG_CLOCK_STM32_HSE_CLOCK

Value of external high-speed clock (HSE).

CONFIG_CLOCK_STM32_LSE

Enable the low-speed external (LSE) clock supplied with a 32.768 kHz crystal resonator oscillator.

CONFIG_CLOCK_STM32_MCO1_DIV

allowed values: 1, 2, 3, 4, 5

CONFIG_CLOCK_STM32_MCO1_SRC_HSE

Use HSE as source of MCO1

CONFIG_CLOCK_STM32_MCO1_SRC_HSI

Use HSI as source of MCO1

CONFIG_CLOCK_STM32_MCO1_SRC_LSE

Use LSE as source of MCO1

CONFIG_CLOCK_STM32_MCO1_SRC_NOCLOCK

MCO1 output disabled, no clock on MCO1

CONFIG_CLOCK_STM32_MCO1_SRC_PLLCLK

Use PLLCLK as source of MCO1

CONFIG_CLOCK_STM32_MCO2_DIV

allowed values: 1, 2, 3, 4, 5

CONFIG_CLOCK_STM32_MCO2_SRC_HSE

Use HSE as source of MCO2

CONFIG_CLOCK_STM32_MCO2_SRC_NOCLOCK

MCO2 output disabled, no clock on MCO2

CONFIG_CLOCK_STM32_MCO2_SRC_PLLCLK

Use PLLCLK as source of MCO2

CONFIG_CLOCK_STM32_MCO2_SRC_PLLI2S

Use PLLI2S as source of MCO2

CONFIG_CLOCK_STM32_MCO2_SRC_SYSCLK

Use SYSCLK as source of MCO2

CONFIG_CLOCK_STM32_MSI_PLL_MODE

Enable hardware auto-calibration with LSE.

CONFIG_CLOCK_STM32_MSI_RANGE

Frequency range of MSI when MSI range is provided in RCC_CR register Range 0: 100kHz Range 1: 200kHz Range 2 around 400 kHz Range 3 around 800 kHz Range 4: 1 MHz Range 5: 2 MHz Range 6: 4 MHz (reset value) Range 7: 8 MHz Range 8: 16 MHz Range 9: 24 MHz Range 10: 32 MHz Range 11: 48 MHz

CONFIG_CLOCK_STM32_PLL_DIVISOR

PLL divisor, allowed values: 2-4.

CONFIG_CLOCK_STM32_PLL_MULTIPLIER

PLL multiplier, allowed values: 2-16. PLL output must not exceed 48MHz.

CONFIG_CLOCK_STM32_PLL_M_DIVISOR

PLLM division factor needs to be set correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter. Allowed values: 2-63

CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER

PLLN multiplier factor needs to be set correctly to ensure that the VCO output frequency is between 100 and 432 MHz, except on STM32F401 where the frequency must be between 192 and 432 MHz. Allowed values: 50-432 (STM32F401: 192-432)

CONFIG_CLOCK_STM32_PLL_PREDIV

PREDIV is PLLSCR clock signal prescaler, allowed values: 1 - 16.

CONFIG_CLOCK_STM32_PLL_PREDIV1

PREDIV is PLLSCR clock signal prescaler, present on STM32F0 SoC having an HSE Oscillator available like the stm32f04xx, stm32f07xx, stm32f09xx and stm32f030xc parts. If configured on a non supported part, the HSI oscillator will be used a default PLL source and this config will be ignored. Allowed values: 1 - 16.

CONFIG_CLOCK_STM32_PLL_P_DIVISOR

PLLP division factor needs to be set correctly to not exceed 84MHz. Allowed values: 2, 4, 6, 8

CONFIG_CLOCK_STM32_PLL_Q_DIVISOR

The USB OTG FS requires a 48MHz clock to work correctly. SDIO and RNG need a frequency lower than or equal to 48 MHz to work correctly. Allowed values: 2-15

CONFIG_CLOCK_STM32_PLL_R_DIVISOR

PLL R Output divisor, allowed values: 1-128.

CONFIG_CLOCK_STM32_PLL_SRC_HSE

Use HSE as source of PLL

CONFIG_CLOCK_STM32_PLL_SRC_HSI

Use HSI as source of PLL

CONFIG_CLOCK_STM32_PLL_SRC_MSI

Use MSI as source of PLL

CONFIG_CLOCK_STM32_PLL_SRC_PLL2

Use PLL2 as source of main PLL. This is equivalent of defining PLL2 as source PREDIV1SCR. If not selected, default source is HSE.

CONFIG_CLOCK_STM32_PLL_XTPRE

Enable this option to enable /2 prescaler on HSE to PLL clock signal

CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE

Use HSE as source of SYSCLK

CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI

Use HSI as source of SYSCLK

CONFIG_CLOCK_STM32_SYSCLK_SRC_MSI

Use MSI as source of SYSCLK

CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL

Use PLL as source of SYSCLK

CONFIG_CONSOLE

Console drivers

CONFIG_CONSOLE_HANDLER

This option enables console input handler allowing to write simple interaction between serial console and the OS.

CONFIG_CONSOLE_HAS_DRIVER

This is an option to be enabled by console drivers to signal that some kind of console exists.

CONFIG_CONSOLE_INPUT_MAX_LINE_LEN

This option can be used to modify the maximum length a console input can be.

CONFIG_CORTEX_M_SYSTICK

This module implements a kernel device driver for the Cortex-M processor SYSTICK timer and provides the standard “system clock driver” interfaces.

CONFIG_COUNTER

Enable support for counter and timer.

CONFIG_COUNTER_CMOS

Counter driver for x86 CMOS/RTC clock

CONFIG_COUNTER_GECKO_RTCC

Enable counter driver based on RTCC module for Silicon Labs Gecko chips.

CONFIG_COUNTER_IMX_EPIT

Enable the IMX EPIT driver.

CONFIG_COUNTER_IMX_EPIT_1

Enable Counter 1.

CONFIG_COUNTER_IMX_EPIT_2

Enable Counter 2.

CONFIG_COUNTER_MCUX_GPT

Enable support for mcux General Purpose Timer (GPT) driver.

CONFIG_COUNTER_MCUX_GPT1

Enable Counter on GPT1

CONFIG_COUNTER_MCUX_GPT2

Enable Counter on GPT2

CONFIG_COUNTER_MCUX_RTC

Enable support for mcux rtc driver.

CONFIG_COUNTER_NRF_RTC

CONFIG_COUNTER_NRF_TIMER

CONFIG_COUNTER_RTC0

Enable Counter on RTC0

CONFIG_COUNTER_RTC1

Enable Counter on RTC1

CONFIG_COUNTER_RTC2

Enable Counter on RTC2

CONFIG_COUNTER_RTC_CUSTOM_TOP_SUPPORT

CONFIG_COUNTER_RTC_STM32

Build RTC driver for STM32 SoCs. Tested on STM32 F3, F4, L4, F7, G4 series

CONFIG_COUNTER_RTC_STM32_CLOCK_LSE

Use LSE as RTC clock

CONFIG_COUNTER_RTC_STM32_CLOCK_LSI

Use LSI as RTC clock

CONFIG_COUNTER_RTC_STM32_LSE_DRIVE_HIGH

Xtal mode higher driving capability

CONFIG_COUNTER_RTC_STM32_LSE_DRIVE_LOW

Xtal mode lower driving capability

CONFIG_COUNTER_RTC_STM32_LSE_DRIVE_MEDIUMHIGH

Xtal mode medium high driving capability

CONFIG_COUNTER_RTC_STM32_LSE_DRIVE_MEDIUMLOW

Xtal mode medium low driving capability

CONFIG_COUNTER_RTC_STM32_LSE_DRIVE_STRENGTH

CONFIG_COUNTER_RTC_WITH_PPI_WRAP

CONFIG_COUNTER_SAM0_TC32

Enable the SAM0 series timer counter (TC) driver in 32-bit wide mode.

CONFIG_COUNTER_SAM0_TC32_0_DIVISOR

CONFIG_COUNTER_SAM0_TC32_0_PRESCALER_1

clock / 1

CONFIG_COUNTER_SAM0_TC32_0_PRESCALER_1024

clock / 1024

CONFIG_COUNTER_SAM0_TC32_0_PRESCALER_16

clock / 16

CONFIG_COUNTER_SAM0_TC32_0_PRESCALER_2

clock / 2

CONFIG_COUNTER_SAM0_TC32_0_PRESCALER_256

clock / 256

CONFIG_COUNTER_SAM0_TC32_0_PRESCALER_4

clock / 4

CONFIG_COUNTER_SAM0_TC32_0_PRESCALER_64

clock / 64

CONFIG_COUNTER_SAM0_TC32_0_PRESCALER_8

clock / 8

CONFIG_COUNTER_SAM0_TC32_2_DIVISOR

CONFIG_COUNTER_SAM0_TC32_2_PRESCALER_1

clock / 1

CONFIG_COUNTER_SAM0_TC32_2_PRESCALER_1024

clock / 1024

CONFIG_COUNTER_SAM0_TC32_2_PRESCALER_16

clock / 16

CONFIG_COUNTER_SAM0_TC32_2_PRESCALER_2

clock / 2

CONFIG_COUNTER_SAM0_TC32_2_PRESCALER_256

clock / 256

CONFIG_COUNTER_SAM0_TC32_2_PRESCALER_4

clock / 4

CONFIG_COUNTER_SAM0_TC32_2_PRESCALER_64

clock / 64

CONFIG_COUNTER_SAM0_TC32_2_PRESCALER_8

clock / 8

CONFIG_COUNTER_SAM0_TC32_4_DIVISOR

CONFIG_COUNTER_SAM0_TC32_4_PRESCALER_1

clock / 1

CONFIG_COUNTER_SAM0_TC32_4_PRESCALER_1024

clock / 1024

CONFIG_COUNTER_SAM0_TC32_4_PRESCALER_16

clock / 16

CONFIG_COUNTER_SAM0_TC32_4_PRESCALER_2

clock / 2

CONFIG_COUNTER_SAM0_TC32_4_PRESCALER_256

clock / 256

CONFIG_COUNTER_SAM0_TC32_4_PRESCALER_4

clock / 4

CONFIG_COUNTER_SAM0_TC32_4_PRESCALER_64

clock / 64

CONFIG_COUNTER_SAM0_TC32_4_PRESCALER_8

clock / 8

CONFIG_COUNTER_SAM0_TC32_6_DIVISOR

CONFIG_COUNTER_SAM0_TC32_6_PRESCALER_1

clock / 1

CONFIG_COUNTER_SAM0_TC32_6_PRESCALER_1024

clock / 1024

CONFIG_COUNTER_SAM0_TC32_6_PRESCALER_16

clock / 16

CONFIG_COUNTER_SAM0_TC32_6_PRESCALER_2

clock / 2

CONFIG_COUNTER_SAM0_TC32_6_PRESCALER_256

clock / 256

CONFIG_COUNTER_SAM0_TC32_6_PRESCALER_4

clock / 4

CONFIG_COUNTER_SAM0_TC32_6_PRESCALER_64

clock / 64

CONFIG_COUNTER_SAM0_TC32_6_PRESCALER_8

clock / 8

CONFIG_COUNTER_TIMER0

Enable Counter on TIMER0

CONFIG_COUNTER_TIMER1

Enable Counter on TIMER1

CONFIG_COUNTER_TIMER2

Enable Counter on TIMER2

CONFIG_COUNTER_TIMER3

Enable Counter on TIMER3

CONFIG_COUNTER_TIMER4

Enable Counter on TIMER4

CONFIG_COUNTER_XEC

Enable counter driver for Microchip XEC MCU series. Such driver will expose the basic timer devices present on the MCU.

CONFIG_CRYPTO

Crypto Drivers [EXPERIMENTAL]

CONFIG_CRYPTO_ATAES132A

Enable Atmel ATAES132A 32k AES Serial EEPROM support.

CONFIG_CRYPTO_ATAES132A_DRV_NAME

Name for the ATAES132A driver which will be used for binding.

CONFIG_CRYPTO_ATAES132A_I2C_ADDR

ATAES132A chip’s I2C address.

CONFIG_CRYPTO_ATAES132A_I2C_PORT_NAME

Master I2C port name through which ATAES132A chip is accessed.

CONFIG_CRYPTO_ATAES132A_I2C_SPEED_FAST

Fast bus speed of up to 400KHz.

CONFIG_CRYPTO_ATAES132A_I2C_SPEED_STANDARD

Standard bis speed of up to 100KHz.

CONFIG_CRYPTO_INIT_PRIORITY

Crypto devices initialization priority.

CONFIG_CRYPTO_MBEDTLS_SHIM

Enable mbedTLS shim layer compliant with crypto APIs. You will need to fill in a relevant value to CONFIG_MBEDTLS_HEAP_SIZE.

CONFIG_CRYPTO_MBEDTLS_SHIM_DRV_NAME

Device name for mbedTLS Pseudo device.

CONFIG_CRYPTO_MBEDTLS_SHIM_MAX_SESSION

This can be used to tweak the amount of sessions the driver can handle in parallel.

CONFIG_CRYPTO_TINYCRYPT_SHIM

Enable TinyCrypt shim layer compliant with crypto APIs.

CONFIG_CRYPTO_TINYCRYPT_SHIM_DRV_NAME

Device name for TinyCrypt Pseudo device.

CONFIG_CRYPTO_TINYCRYPT_SHIM_MAX_SESSION

This can be used to tweak the amount of sessions the driver can handle in parallel.

CONFIG_DHT

Enable driver for the DHT temperature and humidity sensor family.

CONFIG_DISPLAY

Enable display drivers

CONFIG_DISPLAY_MCUX_ELCDIF

Enable support for mcux eLCDIF driver.

CONFIG_DMA

DMA driver Configuration

CONFIG_DMA_0_IRQ_PRI

IRQ Priority for the DMA Controller.

CONFIG_DMA_0_NAME

Device name for DMA Controller 0.

CONFIG_DMA_1_NAME

Device name for DMA Controller 1.

CONFIG_DMA_2_NAME

Device name for DMA Controller 2.

CONFIG_DMA_DW

DesignWare DMA driver.

CONFIG_DMA_NIOS2_MSGDMA

Enable Nios-II Modular Scatter-Gather DMA(MSGDMA) driver.

CONFIG_DMA_SAM0

DMA driver for Atmel SAM0 series MCUs.

CONFIG_DMA_SAM_XDMAC

Enable Atmel SAM MCU Family Direct Memory Access (XDMAC) driver.

CONFIG_DMA_STM32

DMA driver for STM32 series SoCs.

CONFIG_DMA_STM32_V1

Enable DMA support on F2/F4/F7 series SoCs.

CONFIG_DMA_STM32_V2

Enable DMA support on F0/F1/F3/L0/L4 series SoCs.

CONFIG_DUMMY_DISPLAY

Enable dummy display driver compliant with display driver API.

CONFIG_DUMMY_DISPLAY_DEV_NAME

Dummy display device name

CONFIG_DUMMY_DISPLAY_X_RES

X resolution for dummy display

CONFIG_DUMMY_DISPLAY_Y_RES

Y resolution for dummy display

CONFIG_DW_ICTL

Designware Interrupt Controller can be used as a 2nd level interrupt controller which combines several sources of interrupt into one line that is then routed to the 1st level interrupt controller.

CONFIG_DW_ICTL_INIT_PRIORITY

DesignWare Interrupt Controller initialization priority.

CONFIG_DW_ICTL_NAME

Give a name for the instance of Designware Interrupt Controller

CONFIG_DW_ICTL_OFFSET

Parent interrupt number to which DW_ICTL maps

CONFIG_DW_ISR_TBL_OFFSET

This indicates the offset in the SW_ISR_TABLE beginning from where the ISRs for Designware Interrupt Controller are assigned.

CONFIG_EEPROM

Enable support for EEPROM hardware.

CONFIG_EEPROM_AT24

Enable support for Atmel AT24 (and compatible) I2C EEPROMs.

CONFIG_EEPROM_AT25

Enable support for Atmel AT25 (and compatible) SPI EEPROMs.

CONFIG_EEPROM_AT2X

Enable support for Atmel AT2x (and compatible) I2C/SPI EEPROMs.

CONFIG_EEPROM_SHELL

Enable the EEPROM shell with EEPROM related commands.

CONFIG_EEPROM_SHELL_BUFFER_SIZE

Size of the buffer used for EEPROM read/write commands in the EEPROM shell.

CONFIG_EEPROM_SIMULATOR

Enable Simulated EEPROM driver.

CONFIG_EEPROM_SIMULATOR_MIN_READ_TIME_US

Minimum read time (µS)

CONFIG_EEPROM_SIMULATOR_MIN_WRITE_TIME_US

Minimum write time (µS)

CONFIG_EEPROM_SIMULATOR_SIMULATE_TIMING

Enable Simulated hardware timing.

CONFIG_EEPROM_STM32

Enable EEPROM support on the STM32 L0, L1 family of processors.

CONFIG_ENS210

Enable driver for ENS210 Digital Temperature and Humidity sensor.

CONFIG_ENS210_CRC_CHECK

Check the crc value after data reading.

CONFIG_ENS210_MAX_READ_RETRIES

Number of retries when value reading failed, value not valid or crc not ok.

CONFIG_ENS210_MAX_STAT_RETRIES

Number of retries when status reading failed or device not ready.

CONFIG_ENTROPY_CC13XX_CC26XX_ALARM_THRESHOLD

The number of samples detected with repeating patterns before an alarm event is triggered. The associated FRO is automatically shut down.

CONFIG_ENTROPY_CC13XX_CC26XX_POOL_SIZE

The size in bytes of the buffer used to store entropy generated by the hardware. Should be a power of two for high performance.

CONFIG_ENTROPY_CC13XX_CC26XX_RNG

This option enables the driver for the True Random Number Generator (TRNG) for TI SimpleLink CC13xx / CC26xx SoCs.

CONFIG_ENTROPY_CC13XX_CC26XX_SAMPLES_PER_CYCLE

The number of samples used to generate entropy. The time required to generate 64 bits of entropy is determined by the number of FROs enabled, the sampling (system) clock frequency, and this value.

CONFIG_ENTROPY_CC13XX_CC26XX_SHUTDOWN_THRESHOLD

The number of FROs allowed to be shutdown before the driver attempts to take corrective action.

CONFIG_ENTROPY_ESP32_RNG

This option enables the entropy number generator for ESP32 SoCs.

With Wi-Fi and Bluetooth disabled, this will produce pseudo-entropy numbers: noise from these radios are used to feed entropy in this generator.

CONFIG_ENTROPY_GENERATOR

Include entropy drivers in system config.

CONFIG_ENTROPY_HAS_DRIVER

This is an option to be enabled by individual entropy driver to signal that there is a true entropy driver.

CONFIG_ENTROPY_LITEX_RNG

This option enables the RNG module, which is an entropy number generator, based on Pseudo-Random Binary Sequences (PRBS) for LiteX SoC builder

CONFIG_ENTROPY_MCUX_RNGA

This option enables the random number generator accelerator (RNGA) driver based on the MCUX RNGA driver.

CONFIG_ENTROPY_MCUX_TRNG

This option enables the true random number generator (TRNG) driver based on the MCUX TRNG driver.

CONFIG_ENTROPY_NAME

Specify the device name to be used for the ENTROPY driver.

CONFIG_ENTROPY_NRF5_BIAS_CORRECTION

This option enables the RNG bias correction, which guarantees a uniform distribution of 0 and 1. When this option is enabled, the time to generate a byte cannot be guaranteed.

CONFIG_ENTROPY_NRF5_ISR_POOL_SIZE

Buffer length in bytes used to store entropy bytes generated by the hardware to make them ready for ISR consumers. Please note, that size of the pool must be a power of 2.

CONFIG_ENTROPY_NRF5_ISR_THRESHOLD

Low water-mark threshold in bytes to trigger entropy generation for ISR consumers. As soon as the number of available bytes in the buffer goes below this number hardware entropy generation will be started.

CONFIG_ENTROPY_NRF5_PRI

nRF5X RNG IRQ priority.

CONFIG_ENTROPY_NRF5_RNG

This option enables the RNG peripheral, which is a random number generator, based on internal thermal noise, that provides a random 8-bit value to the host when read.

CONFIG_ENTROPY_NRF5_THR_POOL_SIZE

Buffer length in bytes used to store entropy bytes generated by the hardware to make them ready for thread mode consumers. Please note, that size of the pool must be a power of 2.

CONFIG_ENTROPY_NRF5_THR_THRESHOLD

Low water-mark threshold in bytes to trigger entropy generation for thread mode consumers. As soon as the number of available bytes in the buffer goes below this number hardware entropy generation will be started.

CONFIG_ENTROPY_NRF_FORCE_ALT

This option can be enabled to force an alternative implementation of the entropy driver.

CONFIG_ENTROPY_RV32M1_TRNG

This option enables the true random number generator (TRNG) driver based on the RV32M1 TRNG driver.

CONFIG_ENTROPY_SAM_RNG

Enable True Random Number Generator (TRNG) driver for Atmel SAM MCUs.

CONFIG_ENTROPY_STM32_RNG

This option enables the RNG processor, which is a entropy number generator, based on a continuous analog noise, that provides a entropy 32-bit value to the host when read. It is available for F4 (except STM32F401 & STM32F411), L4, F7 and G4 series.

CONFIG_ESPI

Enable ESPI Driver.

CONFIG_ESPI_AUTOMATIC_WARNING_ACKNOWLEDGE

Enable automatic acknowledge from eSPI slave towards eSPI host whenever it receives suspend or reset warning. If this is disabled, it means the app wants to be give the opportunity to prepare for either HOST suspend or reset.

CONFIG_ESPI_FLASH_CHANNEL

eSPI Controller supports flash channel.

CONFIG_ESPI_INIT_PRIORITY

Driver initialization priority for eSPI driver.

CONFIG_ESPI_OOB_CHANNEL

eSPI Controller supports OOB channel.

CONFIG_ESPI_PERIPHERAL_8042_KBC

Enables 8042 keyboard controller over eSPI peripheral channel.

CONFIG_ESPI_PERIPHERAL_CHANNEL

eSPI Controller supports peripheral channel.

CONFIG_ESPI_PERIPHERAL_DEBUG_PORT_80

Enables debug Port 80 over eSPI peripheral channel.

CONFIG_ESPI_PERIPHERAL_HOST_IO

Enables ACPI Host I/O over eSPI peripheral channel.

CONFIG_ESPI_PERIPHERAL_PORT_92

Enables legacy Port 92 over eSPI peripheral channel.

CONFIG_ESPI_PERIPHERAL_UART

Enables UART over eSPI peripheral channel.

CONFIG_ESPI_PERIPHERAL_UART_SOC_MAPPING

This tells the driver to which SoC UART to direct the UART traffic send over eSPI from host.

CONFIG_ESPI_SLAVE

Enables eSPI driver in slave mode.

CONFIG_ESPI_VWIRE_CHANNEL

eSPI Controller supports virtual wires channel.

CONFIG_ESPI_XEC

Enable the Microchip XEC ESPI driver.

CONFIG_ETH_E1000

Enable Intel(R) PRO/1000 Gigabit Ethernet driver.

CONFIG_ETH_E1000_VERBOSE_DEBUG

Enabling this will turn on the hexdump of the received and sent frames. Do not leave on for production.

CONFIG_ETH_ENC28J60

ENC28J60C Stand-Alone Ethernet Controller with SPI Interface

CONFIG_ETH_ENC28J60_0

Include port 0 driver

CONFIG_ETH_ENC28J60_0_FULL_DUPLEX

Enable Full Duplex. Device is configured half duplex when disabled.

CONFIG_ETH_ENC28J60_0_GPIO_SPI_CS

This option is useful if one needs to manage SPI CS through a GPIO pin to by-pass the SPI controller’s CS logic.

CONFIG_ETH_ENC28J60_RX_THREAD_PRIO

Priority level for internal thread which is ran for incoming packet processing.

CONFIG_ETH_ENC28J60_RX_THREAD_STACK_SIZE

Size of the stack used for internal thread which is ran for incoming packet processing.

CONFIG_ETH_ENC28J60_TIMEOUT

Given timeout in milliseconds. Maximum amount of time that the driver will wait from the IP stack to get a memory buffer before the Ethernet frame is dropped.

CONFIG_ETH_ENC424J600

ENC424J600C Stand-Alone Ethernet Controller with SPI Interface

CONFIG_ETH_ENC424J600_0_GPIO_SPI_CS

This option is useful if one needs to manage SPI CS through a GPIO pin to by-pass the SPI controller’s CS logic.

CONFIG_ETH_ENC424J600_RX_THREAD_PRIO

Priority level for internal thread which is ran for incoming packet processing.

CONFIG_ETH_ENC424J600_RX_THREAD_STACK_SIZE

Size of the stack used for internal thread which is ran for incoming packet processing.

CONFIG_ETH_ENC424J600_TIMEOUT

Given timeout in milliseconds. Maximum amount of time that the driver will wait from the IP stack to get a memory buffer before the Ethernet frame is dropped.

CONFIG_ETH_GECKO

Enable Ethernet driver for Silicon Labs Gecko chips.

CONFIG_ETH_GECKO_CARRIER_CHECK_RX_IDLE_TIMEOUT_MS

Set the RX idle timeout period in milliseconds after which the PHY’s carrier status is re-evaluated.

CONFIG_ETH_GECKO_IRQ_PRI

IRQ priority of Ethernet device

CONFIG_ETH_GECKO_MAC0

MAC Address Byte 0

CONFIG_ETH_GECKO_MAC1

MAC Address Byte 1

CONFIG_ETH_GECKO_MAC2

MAC Address Byte 2

CONFIG_ETH_GECKO_MAC3

MAC Address Byte 3

CONFIG_ETH_GECKO_MAC4

MAC Address Byte 4

CONFIG_ETH_GECKO_MAC5

MAC Address Byte 5

CONFIG_ETH_GECKO_MAC_MANUAL

Assign an arbitrary MAC address.

CONFIG_ETH_GECKO_NAME

Device name allows user to obtain a handle to the device object required by all driver API functions. Device name has to be unique.

CONFIG_ETH_GECKO_RANDOM_MAC

Generate a random MAC address dynamically.

CONFIG_ETH_GECKO_RX_THREAD_PRIO

RX thread priority

CONFIG_ETH_GECKO_RX_THREAD_STACK_SIZE

RX thread stack size

CONFIG_ETH_INIT_PRIORITY

Ethernet device driver initialization priority. Do not mess with it unless you know what you are doing. Note that the priority needs to be lower than the net stack so that it can start before the networking sub-system.

CONFIG_ETH_LITEETH

LiteEth Ethernet core driver

CONFIG_ETH_LITEETH_0

LiteEth Ethernet port 0

CONFIG_ETH_LITEETH_0_IRQ_PRI

IRQ priority

CONFIG_ETH_LITEETH_0_RANDOM_MAC

Generate a random MAC address dynamically.

CONFIG_ETH_MCUX

Enable MCUX Ethernet driver. Note, this driver performs one shot PHY setup. There is no support for PHY disconnect, reconnect or configuration change.

CONFIG_ETH_MCUX_0

Include port 0 driver

CONFIG_ETH_MCUX_0_MANUAL_MAC

Manual MAC address

CONFIG_ETH_MCUX_0_RANDOM_MAC

Generate a random MAC address dynamically on each reboot. Note that using this choice and rebooting a board may leave stale MAC address in peers’ ARP caches and lead to issues and delays in communication. (Use “ip neigh flush all” on Linux peers to clear ARP cache.)

CONFIG_ETH_MCUX_0_UNIQUE_MAC

Generate MAC address from MCU’s unique identification register.

CONFIG_ETH_MCUX_HW_ACCELERATION

Enable hardware acceleration for the following: - IPv4, UDP and TCP checksum (both Rx and Tx)

CONFIG_ETH_MCUX_PHY_EXTRA_DEBUG

Enable additional PHY related debug information related to PHY status polling.

CONFIG_ETH_MCUX_PHY_TICK_MS

Set the PHY status polling period.

CONFIG_ETH_MCUX_PROMISCUOUS_MODE

Place the Ethernet receiver in promiscuous mode. This may be useful for debugging and not needed for normal work.

CONFIG_ETH_MCUX_PTP_CLOCK_SRC_HZ

Set the frequency in Hz sourced to the PTP timer. If the value is set properly, the timer will be accurate.

CONFIG_ETH_MCUX_PTP_RX_BUFFERS

Set the number of RX buffers provided to the MCUX driver to store timestamps.

CONFIG_ETH_MCUX_PTP_TX_BUFFERS

Set the number of TX buffers provided to the MCUX driver to store timestamps.

CONFIG_ETH_MCUX_RX_BUFFERS

Set the number of RX buffers provided to the MCUX driver.

CONFIG_ETH_MCUX_TX_BUFFERS

Set the number of TX buffers provided to the MCUX driver.

CONFIG_ETH_NATIVE_POSIX

Enable native posix ethernet driver. Note, this driver is run inside a process in your host system.

CONFIG_ETH_NATIVE_POSIX_DEV_NAME

This option sets the TUN/TAP device name in your host system.

CONFIG_ETH_NATIVE_POSIX_DRV_NAME

This option sets the driver name and name of the network interface in your host system.

CONFIG_ETH_NATIVE_POSIX_MAC_ADDR

Specify a MAC address for the ethernet interface in the form of six hex 8-bit chars separated by colons (e.g.: aa:33:cc:22:e2:c0). The default is an empty string, which means the code will make 00:00:5E:00:53:XX, where XX will be random.

CONFIG_ETH_NATIVE_POSIX_PTP_CLOCK

Enable PTP clock support.

CONFIG_ETH_NATIVE_POSIX_RANDOM_MAC

Generate a random MAC address dynamically.

CONFIG_ETH_NATIVE_POSIX_SETUP_SCRIPT

This option sets the name of the script that is run when the host TAP network interface is created. The script should setup IP addresses etc. for the host TAP network interface. The default script accepts following options: -i|–interface <network interface name>, default is zeth -f|–file <config file name>, default is net_setup_host.conf If needed, you can add these options to this script name option. Note that the driver will add -i option with the value of CONFIG_ETH_NATIVE_POSIX_DRV_NAME option to the end of the options list when calling the host setup script.

CONFIG_ETH_NATIVE_POSIX_STARTUP_AUTOMATIC

If set, the native_posix ethernet driver will set up the network interface, requiring zephyr.exe to be run with root privileges (needed to create and configure the TAP device). If not set (the default and recommended way), the network interface must be set up manually using net-setup.sh (from the net-tools project repo). The zephyr.exe program can then be run as a non-root user.

CONFIG_ETH_NATIVE_POSIX_STARTUP_SCRIPT

This option sets the name of the script that is run when the host TAP network interface is created and setup script has been run. The startup script could launch e.g., wireshark to capture the network traffic for the freshly started network interface. Note that the network interface name CONFIG_ETH_NATIVE_POSIX_DRV_NAME is appended at the end of this startup script name. Example script for starting wireshark is provided in ${ZEPHYR_BASE}/samples/net/eth_native_posix/net_start_wireshark.sh file.

CONFIG_ETH_NATIVE_POSIX_STARTUP_SCRIPT_USER

By default the startup script is run as a root user. Set here the username to run the script if running it as a root user is not desired. Note that this setting is only for startup script and not for the setup script. The setup script needs to be run always as a root user.

CONFIG_ETH_NATIVE_POSIX_VLAN_TAG_STRIP

Native posix ethernet driver will strip of VLAN tag from Rx Ethernet frames and sets tag information in net packet metadata.

CONFIG_ETH_NIC_MODEL

Tells what Qemu network model to use. This value is given as a parameter to -nic qemu command line option.

CONFIG_ETH_SAM_GMAC

Enable Atmel SAM MCU Family Ethernet driver.

CONFIG_ETH_SAM_GMAC_BUF_RX_COUNT

Number of network buffers that will be permanently allocated by the Ethernet driver. These buffers are used in receive path. They are preallocated by the driver and made available to the GMAC module to be filled in with incoming data. Their number has to be large enough to fit at least one complete Ethernet frame. SAM ETH driver will always allocate that amount of buffers for itself thus reducing the NET_BUF_RX_COUNT which is a total amount of RX data buffers used by the whole networking stack. One has to ensure that NET_PKT_RX_COUNT is large enough to fit at least two Ethernet frames: one being received by the GMAC module and the other being processed by the higher layer networking stack.

CONFIG_ETH_SAM_GMAC_FORCED_QUEUE

Which queue to force the routing to. This affects both the TX and RX queues setup.

CONFIG_ETH_SAM_GMAC_FORCE_QUEUE

This option is meant to be used only for debugging. Use it to force all traffic to be routed through a specific hardware queue. With this enabled it is easier to verify whether the chosen hardware queue actually works. This works only if there are four or fewer RX traffic classes enabled, as the SAM GMAC hardware supports screening up to four traffic classes.

CONFIG_ETH_SAM_GMAC_IRQ_PRI

IRQ priority of Ethernet device

CONFIG_ETH_SAM_GMAC_MAC0

MAC Address Byte 0

CONFIG_ETH_SAM_GMAC_MAC1

MAC Address Byte 1

CONFIG_ETH_SAM_GMAC_MAC2

MAC Address Byte 2

CONFIG_ETH_SAM_GMAC_MAC3

MAC Address Byte 3

CONFIG_ETH_SAM_GMAC_MAC4

MAC Address Byte 4

CONFIG_ETH_SAM_GMAC_MAC5

MAC Address Byte 5

CONFIG_ETH_SAM_GMAC_MAC_I2C_DEV_NAME

Device name, e.g. I2C_0, of an I2C bus driver device. It is required to obtain handle to the I2C device object.

CONFIG_ETH_SAM_GMAC_MAC_I2C_EEPROM

Read MAC address from an I2C EEPROM.

CONFIG_ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS

Internal address of the EEPROM chip where the MAC address is stored. Chips with 1 to 4 byte internal address size are supported. Address size has to be configured in a separate Kconfig option.

CONFIG_ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS_SIZE

Size (in bytes) of the internal EEPROM address.

CONFIG_ETH_SAM_GMAC_MAC_I2C_SLAVE_ADDRESS

I2C 7-bit address of the EEPROM chip.

CONFIG_ETH_SAM_GMAC_MAC_MANUAL

Assign an arbitrary MAC address.

CONFIG_ETH_SAM_GMAC_MII

MII

CONFIG_ETH_SAM_GMAC_NAME

Device name allows user to obtain a handle to the device object required by all driver API functions. Device name has to be unique.

CONFIG_ETH_SAM_GMAC_PHY_ADDR

GMAC PHY Address as used by IEEE 802.3, Section 2 MII compatible PHY transceivers. If you have a single PHY on board it is safe to leave it at 0 which is the broadcast address.

CONFIG_ETH_SAM_GMAC_QUEUES

Select the number of hardware queues used by the driver. Packets will be routed to appropriate queues based on their priority.

CONFIG_ETH_SAM_GMAC_RANDOM_MAC

Generate a random MAC address dynamically.

CONFIG_ETH_SAM_GMAC_RMII

RMII

CONFIG_ETH_SMSC911X

Enable driver for SMSC/LAN911x/9220 family of chips.

CONFIG_ETH_STELLARIS

Stellaris on-board Ethernet Controller

CONFIG_ETH_STM32_CARRIER_CHECK_RX_IDLE_TIMEOUT_MS

Set the RX idle timeout period in milliseconds after which the PHY’s carrier status is re-evaluated.

CONFIG_ETH_STM32_HAL

Enable STM32 HAL based Ethernet driver. It is available for all Ethernet enabled variants of the F2, F4 and F7 series.

CONFIG_ETH_STM32_HAL_IRQ_PRI

IRQ priority

CONFIG_ETH_STM32_HAL_MAC3

This is the byte 3 of the MAC address.

CONFIG_ETH_STM32_HAL_MAC4

This is the byte 4 of the MAC address.

CONFIG_ETH_STM32_HAL_MAC5

This is the byte 5 of the MAC address.

CONFIG_ETH_STM32_HAL_MII

Use the MII physical interface instead of RMII.

CONFIG_ETH_STM32_HAL_NAME

Device name

CONFIG_ETH_STM32_HAL_PHY_ADDRESS

The phy address to use.

CONFIG_ETH_STM32_HAL_RANDOM_MAC

Generate a random MAC address dynamically.

CONFIG_ETH_STM32_HAL_RX_THREAD_PRIO

RX thread priority

CONFIG_ETH_STM32_HAL_RX_THREAD_STACK_SIZE

RX thread stack size

CONFIG_ETH_STM32_HAL_USE_DTCM_FOR_DMA_BUFFER

When this option is activated, the buffers for DMA transfer are moved from SRAM to the DTCM (Data Tightly Coupled Memory).

CONFIG_EXTI_STM32

Enable EXTI driver for STM32 line of MCUs

CONFIG_EXTI_STM32_EXTI0_IRQ_PRI

IRQ priority of EXTI0 interrupt

CONFIG_EXTI_STM32_EXTI10_IRQ_PRI

IRQ priority of EXTI10 interrupt

CONFIG_EXTI_STM32_EXTI11_IRQ_PRI

IRQ priority of EXTI11 interrupt

CONFIG_EXTI_STM32_EXTI12_IRQ_PRI

IRQ priority of EXTI12 interrupt

CONFIG_EXTI_STM32_EXTI13_IRQ_PRI

IRQ priority of EXTI13 interrupt

CONFIG_EXTI_STM32_EXTI14_IRQ_PRI

IRQ priority of EXTI14 interrupt

CONFIG_EXTI_STM32_EXTI15_10_IRQ_PRI

IRQ priority of EXTI15:10 interrupt

CONFIG_EXTI_STM32_EXTI15_4_IRQ_PRI

IRQ priority of EXTI15:4 interrupt

CONFIG_EXTI_STM32_EXTI15_IRQ_PRI

IRQ priority of EXTI15 interrupt

CONFIG_EXTI_STM32_EXTI1_0_IRQ_PRI

IRQ priority of EXTI1:0 interrupt

CONFIG_EXTI_STM32_EXTI1_IRQ_PRI

IRQ priority of EXTI1 interrupt

CONFIG_EXTI_STM32_EXTI2_IRQ_PRI

IRQ priority of EXTI2 interrupt

CONFIG_EXTI_STM32_EXTI3_2_IRQ_PRI

IRQ priority of EXTI3:2 interrupt

CONFIG_EXTI_STM32_EXTI3_IRQ_PRI

IRQ priority of EXTI3 interrupt

CONFIG_EXTI_STM32_EXTI4_IRQ_PRI

IRQ priority of EXTI4 interrupt

CONFIG_EXTI_STM32_EXTI5_IRQ_PRI

IRQ priority of EXTI5 interrupt

CONFIG_EXTI_STM32_EXTI6_IRQ_PRI

IRQ priority of EXTI6 interrupt

CONFIG_EXTI_STM32_EXTI7_IRQ_PRI

IRQ priority of EXTI7 interrupt

CONFIG_EXTI_STM32_EXTI8_IRQ_PRI

IRQ priority of EXTI8 interrupt

CONFIG_EXTI_STM32_EXTI9_5_IRQ_PRI

IRQ priority of EXTI9:5 interrupt

CONFIG_EXTI_STM32_EXTI9_IRQ_PRI

IRQ priority of EXTI9 interrupt

CONFIG_EXTI_STM32_LPTIM1_IRQ_PRI

IRQ priority of LPTIM1 interrupt

CONFIG_EXTI_STM32_OTG_FS_WKUP_IRQ_PRI

IRQ priority of USB OTG FS Wake interrupt

CONFIG_EXTI_STM32_PVD_IRQ_PRI

IRQ priority of RVD Through interrupt

CONFIG_EXTI_STM32_RTC_WKUP_IRQ_PRI

IRQ priority of RTC Wake Up interrupt

CONFIG_EXTI_STM32_TAMP_STAMP_IRQ_PRI

IRQ priority of Tamper and Timestamp interrupt

CONFIG_FAKE_ENTROPY_NATIVE_POSIX

This option enables the test random number generator for the native_posix board (ARCH_POSIX). This is based on the host random() API. Note that this entropy generator is only meant for test purposes and does not generate real entropy. It actually generates always the same sequence of random numbers if initialized with the same seed.

CONFIG_FLASH

Enable support for the flash hardware.

CONFIG_FLASH_HAS_DRIVER_ENABLED

This option is enabled when any flash driver is enabled.

CONFIG_FLASH_HAS_PAGE_LAYOUT

This option is enabled when the SoC flash driver supports retrieving the layout of flash memory pages.

CONFIG_FLASH_NRF_FORCE_ALT

This option can be enabled to force an alternative implementation of the flash driver.

CONFIG_FLASH_PAGE_LAYOUT

Enables API for retrieving the layout of flash memory pages.

CONFIG_FLASH_SHELL

Enable the flash shell with flash related commands such as test, write, read and erase.

CONFIG_FLASH_SIMULATOR

Enable the flash simulator.

CONFIG_FLASH_SIMULATOR_DOUBLE_WRITES

If selected, writing to a non-erased program unit will succeed, otherwise, it will return an error. Keep in mind that write operations can only pull bits to zero, regardless.

CONFIG_FLASH_SIMULATOR_ERASE_PROTECT

If selected, turning on write protection will also prevent erasing.

CONFIG_FLASH_SIMULATOR_MIN_ERASE_TIME_US

Minimum erase time (µS)

CONFIG_FLASH_SIMULATOR_MIN_READ_TIME_US

Minimum read time (µS)

CONFIG_FLASH_SIMULATOR_MIN_WRITE_TIME_US

Minimum write time (µS)

CONFIG_FLASH_SIMULATOR_SIMULATE_TIMING

Enable hardware timing simulation

CONFIG_FLASH_SIMULATOR_STAT_PAGE_COUNT

Only up to this number of beginning pages will be tracked while catching dedicated flash operations and thresholds. This number is not automatic because implementation uses UNTIL_REPEAT() macro, which is limited to take explicitly number of iterations. This is why it’s not possible to calculate the number of pages with preprocessor using DT properties.

CONFIG_FLASH_SIMULATOR_UNALIGNED_READ

If selected, the reading operation does not check if access is aligned. Disable this option only if you want to simulate a specific FLASH interface that requires aligned read access.

CONFIG_FLEXPWM1_PWM0

Enable output for FLEXPWM1_PWM0 in the driver. Say y here if you want to use FLEXPWM1_PWM0 output.

CONFIG_FLEXPWM1_PWM1

Enable output for FLEXPWM1_PWM1 in the driver. Say y here if you want to use FLEXPWM1_PWM1 output.

CONFIG_FLEXPWM1_PWM2

Enable output for FLEXPWM1_PWM2 in the driver. Say y here if you want to use FLEXPWM1_PWM2 output.

CONFIG_FLEXPWM1_PWM3

Enable output for FLEXPWM1_PWM3 in the driver. Say y here if you want to use FLEXPWM1_PWM3 output.

CONFIG_FLEXPWM2_PWM0

Enable output for FLEXPWM2_PWM0 in the driver. Say y here if you want to use FLEXPWM2_PWM0 output.

CONFIG_FLEXPWM2_PWM1

Enable output for FLEXPWM2_PWM1 in the driver. Say y here if you want to use FLEXPWM2_PWM1 output.

CONFIG_FLEXPWM2_PWM2

Enable output for FLEXPWM2_PWM2 in the driver. Say y here if you want to use FLEXPWM2_PWM2 output.

CONFIG_FLEXPWM2_PWM3

Enable output for FLEXPWM2_PWM3 in the driver. Say y here if you want to use FLEXPWM2_PWM3 output.

CONFIG_FLEXPWM3_PWM0

Enable output for FLEXPWM3_PWM0 in the driver. Say y here if you want to use FLEXPWM3_PWM0 output.

CONFIG_FLEXPWM3_PWM1

Enable output for FLEXPWM3_PWM1 in the driver. Say y here if you want to use FLEXPWM3_PWM1 output.

CONFIG_FLEXPWM3_PWM2

Enable output for FLEXPWM3_PWM2 in the driver. Say y here if you want to use FLEXPWM3_PWM2 output.

CONFIG_FLEXPWM3_PWM3

Enable output for FLEXPWM3_PWM3 in the driver. Say y here if you want to use FLEXPWM3_PWM3 output.

CONFIG_FLEXPWM4_PWM0

Enable output for FLEXPWM4_PWM0 in the driver. Say y here if you want to use FLEXPWM4_PWM0 output.

CONFIG_FLEXPWM4_PWM1

Enable output for FLEXPWM4_PWM1 in the driver. Say y here if you want to use FLEXPWM4_PWM1 output.

CONFIG_FLEXPWM4_PWM2

Enable output for FLEXPWM4_PWM2 in the driver. Say y here if you want to use FLEXPWM4_PWM2 output.

CONFIG_FLEXPWM4_PWM3

Enable output for FLEXPWM4_PWM3 in the driver. Say y here if you want to use FLEXPWM4_PWM3 output.

CONFIG_FRAMEBUF_DISPLAY

Enable framebuffer-based display ‘helper’ driver.

CONFIG_FXAS21002

Enable driver for the FXAS21002 gyroscope

CONFIG_FXAS21002_DR

Selects the output data rate 0: 800 Hz 1: 400 Hz 2: 200 Hz 3: 100 Hz 4: 50 Hz 5: 25 Hz 6: 12.5 Hz 7: 12.5 Hz

CONFIG_FXAS21002_DRDY_INT1

Say Y to route data ready interrupt to INT1 pin. Say N to route to INT2 pin.

CONFIG_FXAS21002_RANGE

Selects the full scale range 0: +/-2000 dps (62.5 mdps/LSB) 1: +/-1000 dps (31.25 mdps/LSB) 2: +/-500 dps (15.625 mdps/LSB) 3: +/-250 dps (7.8125 mdps/LSB)

CONFIG_FXAS21002_THREAD_PRIORITY

Own thread priority

CONFIG_FXAS21002_THREAD_STACK_SIZE

Own thread stack size

CONFIG_FXAS21002_TRIGGER

CONFIG_FXAS21002_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_FXAS21002_TRIGGER_NONE

No trigger

CONFIG_FXAS21002_TRIGGER_OWN_THREAD

Use own thread

CONFIG_FXAS21002_WHOAMI

The datasheet defines the value of the WHOAMI register, but some pre-production devices can have a different value. It is unlikely you should need to change this configuration option from the default.

CONFIG_FXOS8700

Enable driver for the FXOS8700 accelerometer/magnetometer. The driver also supports MMA8451Q, MMA8652FC and MMA8653FC accelerometers. If the driver is used with one of these accelerometers then the Accelerometer-only mode should be selected.”

CONFIG_FXOS8700_DRDY_INT1

Say Y to route data ready interrupt to INT1 pin. Say N to route to INT2 pin.

CONFIG_FXOS8700_MODE_ACCEL

Accelerometer-only mode

CONFIG_FXOS8700_MODE_HYBRID

Hybrid (accel+mag) mode

CONFIG_FXOS8700_MODE_MAGN

Magnetometer-only mode

CONFIG_FXOS8700_MOTION

Enable motion detection

CONFIG_FXOS8700_MOTION_INT1

Say Y to route motion interrupt to INT1 pin. Say N to route to INT2 pin.

CONFIG_FXOS8700_PM_HIGH_RESOLUTION

High resolution power mode

CONFIG_FXOS8700_PM_LOW_NOISE_LOW_POWER

Low noise low power mode

CONFIG_FXOS8700_PM_LOW_POWER

Low power mode

CONFIG_FXOS8700_PM_NORMAL

Normal power mode

CONFIG_FXOS8700_PULSE

Enable pulse detection

CONFIG_FXOS8700_PULSE_CFG

Pulse configuration register

CONFIG_FXOS8700_PULSE_INT1

Say Y to route pulse interrupt to INT1 pin. Say N to route to INT2 pin.

CONFIG_FXOS8700_PULSE_LTCY

The time interval that starts after the first pulse detection where the pulse-detection function ignores the start of a new pulse. The resolution depends upon the sample rate (ODR) and the high-pass filter configuration (HP_FILTER_CUTOFF[pls_hpf_en]). For ODR=800 Hz and pls_hpf_en=0, the resolution is 1.25 ms/LSB.

CONFIG_FXOS8700_PULSE_THSX

Threshold to start the pulse-event detection procedure on the X-axis. Threshold values for each axis are unsigned 7-bit numbers with a fixed resolution of 0.063 g/LSB, corresponding to an 8g acceleration full-scale range.

CONFIG_FXOS8700_PULSE_THSY

Threshold to start the pulse-event detection procedure on the Y-axis. Threshold values for each axis are unsigned 7-bit numbers with a fixed resolution of 0.063 g/LSB, corresponding to an 8g acceleration full-scale range.

CONFIG_FXOS8700_PULSE_THSZ

Threshold to start the pulse-event detection procedure on the Z-axis. Threshold values for each axis are unsigned 7-bit numbers with a fixed resolution of 0.063 g/LSB, corresponding to an 8g acceleration full-scale range.

CONFIG_FXOS8700_PULSE_TMLT

The maximum time interval that can elapse between the start of the acceleration on the selected channel exceeding the specified threshold and the end when the channel acceleration goes back below the specified threshold. The resolution depends upon the sample rate (ODR) and the high-pass filter configuration (HP_FILTER_CUTOFF[pls_hpf_en]). For ODR=800 Hz and pls_hpf_en=0, the resolution is 0.625 ms/LSB.

CONFIG_FXOS8700_PULSE_WIND

The maximum interval of time that can elapse after the end of the latency interval in which the start of the second pulse event must be detected provided the device has been configured for double pulse detection. The detected second pulse width must be shorter than the time limit constraint specified by the PULSE_TMLT register, but the end of the double pulse need not finish within the time specified by the PULSE_WIND register. The resolution depends upon the sample rate (ODR) and the high-pass filter configuration (HP_FILTER_CUTOFF[pls_hpf_en]). For ODR=800 Hz and pls_hpf_en=0, the resolution is 1.25 ms/LSB.

CONFIG_FXOS8700_RANGE_2G

2g (0.244 mg/LSB)

CONFIG_FXOS8700_RANGE_4G

4g (0.488 mg/LSB)

CONFIG_FXOS8700_RANGE_8G

8g (0.976 mg/LSB)

CONFIG_FXOS8700_TEMP

Enable the temperature sensor. Note that the temperature sensor is uncalibrated and its output for a given temperature may vary from one device to the next.

CONFIG_FXOS8700_THREAD_PRIORITY

Own thread priority

CONFIG_FXOS8700_THREAD_STACK_SIZE

Own thread stack size

CONFIG_FXOS8700_TRIGGER

CONFIG_FXOS8700_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_FXOS8700_TRIGGER_NONE

No trigger

CONFIG_FXOS8700_TRIGGER_OWN_THREAD

Use own thread

CONFIG_GIC

CONFIG_GIC_V1

The ARM Generic Interrupt Controller v1 (e.g. PL390) works with the ARM Cortex-family processors.

CONFIG_GIC_V2

The ARM Generic Interrupt Controller v2 (e.g. GIC-400) works with the ARM Cortex-family processors.

CONFIG_GIC_V3

The ARM Generic Interrupt Controller v3 (e.g. GIC-500 and GIC-600) works with the ARM Cortex-family processors.

CONFIG_GIC_VER

CONFIG_GPIO

Include GPIO drivers in system config

CONFIG_GPIO_A_STELLARIS

Enable GPIO port A support

CONFIG_GPIO_B_STELLARIS

Enable GPIO port B support

CONFIG_GPIO_CC13XX_CC26XX

Enable the TI SimpleLink CC13xx / CC26xx GPIO driver.

CONFIG_GPIO_CC32XX

Enable the GPIO driver on TI SimpleLink CC32xx boards

CONFIG_GPIO_CC32XX_A0

Include support for the GPIO port A0.

CONFIG_GPIO_CC32XX_A1

Include support for the GPIO port A1.

CONFIG_GPIO_CC32XX_A2

Include support for the GPIO port A2.

CONFIG_GPIO_CC32XX_A3

Include support for the GPIO port A3.

CONFIG_GPIO_CMSDK_AHB

Enable config options to support the ARM CMSDK GPIO controllers.

Says n if not sure.

CONFIG_GPIO_CMSDK_AHB_PORT0

Build the driver to utilize GPIO controller Port 0.

CONFIG_GPIO_CMSDK_AHB_PORT0_DEV_NAME

Device name for Port 0.

CONFIG_GPIO_CMSDK_AHB_PORT0_IRQ_PRI

Interrupt priority for Port 0.

CONFIG_GPIO_CMSDK_AHB_PORT1

Build the driver to utilize GPIO controller Port 1.

CONFIG_GPIO_CMSDK_AHB_PORT1_DEV_NAME

Device name for Port 1.

CONFIG_GPIO_CMSDK_AHB_PORT1_IRQ_PRI

Interrupt priority for Port 1.

CONFIG_GPIO_CMSDK_AHB_PORT2

Build the driver to utilize GPIO controller Port 2.

CONFIG_GPIO_CMSDK_AHB_PORT2_DEV_NAME

Device name for Port 2.

CONFIG_GPIO_CMSDK_AHB_PORT2_IRQ_PRI

Interrupt priority for Port 2.

CONFIG_GPIO_CMSDK_AHB_PORT3

Build the driver to utilize GPIO controller Port 3.

CONFIG_GPIO_CMSDK_AHB_PORT3_DEV_NAME

Device name for Port 3.

CONFIG_GPIO_CMSDK_AHB_PORT3_IRQ_PRI

Interrupt priority for Port 3.

CONFIG_GPIO_C_STELLARIS

Enable GPIO port C support

CONFIG_GPIO_DW

Enable driver for Designware GPIO

CONFIG_GPIO_DW_0

Include Designware GPIO driver

CONFIG_GPIO_DW_0_CLOCK_GATE_SUBSYS

Clock controller’s subsystem

CONFIG_GPIO_DW_0_IRQ_DIRECT

When interrupts fire, the driver’s ISR function is being called directly.

CONFIG_GPIO_DW_0_IRQ_PRI

IRQ priority

CONFIG_GPIO_DW_0_IRQ_SHARED

When interrupts fire, the shared IRQ driver is notified. Then the shared IRQ driver dispatches the interrupt to other drivers.

CONFIG_GPIO_DW_0_NAME

Driver name

CONFIG_GPIO_DW_1

Include Designware GPIO driver

CONFIG_GPIO_DW_1_CLOCK_GATE_SUBSYS

Clock controller’s subsystem

CONFIG_GPIO_DW_1_IRQ_DIRECT

When interrupts fire, the driver’s ISR function is being called directly.

CONFIG_GPIO_DW_1_IRQ_PRI

IRQ priority

CONFIG_GPIO_DW_1_IRQ_SHARED

When interrupts fire, the shared IRQ driver is notified. Then the shared IRQ driver dispatches the interrupt to other drivers.

CONFIG_GPIO_DW_1_NAME

Driver name

CONFIG_GPIO_DW_2

Include Designware GPIO driver

CONFIG_GPIO_DW_2_CLOCK_GATE_SUBSYS

Clock controller’s subsystem

CONFIG_GPIO_DW_2_IRQ_DIRECT

When interrupts fire, the driver’s ISR function is being called directly.

CONFIG_GPIO_DW_2_IRQ_PRI

IRQ priority

CONFIG_GPIO_DW_2_IRQ_SHARED

When interrupts fire, the shared IRQ driver is notified. Then the shared IRQ driver dispatches the interrupt to other drivers.

CONFIG_GPIO_DW_2_NAME

Driver name

CONFIG_GPIO_DW_3

Include Designware GPIO driver

CONFIG_GPIO_DW_3_CLOCK_GATE_SUBSYS

Clock controller’s subsystem

CONFIG_GPIO_DW_3_IRQ_DIRECT

When interrupts fire, the driver’s ISR function is being called directly.

CONFIG_GPIO_DW_3_IRQ_PRI

IRQ priority

CONFIG_GPIO_DW_3_IRQ_SHARED

When interrupts fire, the shared IRQ driver is notified. Then the shared IRQ driver dispatches the interrupt to other drivers.

CONFIG_GPIO_DW_3_NAME

Driver name

CONFIG_GPIO_DW_CLOCK_GATE

Enable clock gating

CONFIG_GPIO_DW_CLOCK_GATE_DRV_NAME

CONFIG_GPIO_DW_INIT_PRIORITY

Device driver initialization priority.

CONFIG_GPIO_DW_SHARED_IRQ

CONFIG_GPIO_D_STELLARIS

Enable GPIO port D support

CONFIG_GPIO_ESP32

Enables the ESP32 GPIO driver

CONFIG_GPIO_ESP32_0

Include support for GPIO pins 0-31 on the ESP32.

CONFIG_GPIO_ESP32_1

Include support for GPIO pins 32-39 on the ESP32.

CONFIG_GPIO_ESP32_IRQ

IRQ line for ESP32 GPIO pins

CONFIG_GPIO_E_STELLARIS

Enable GPIO port E support

CONFIG_GPIO_F_STELLARIS

Enable GPIO port F support

CONFIG_GPIO_GECKO

Enable the Gecko gpio driver.

CONFIG_GPIO_GECKO_COMMON_INIT_PRIORITY

Common initialization priority

CONFIG_GPIO_GECKO_PORTA

Enable Port A.

CONFIG_GPIO_GECKO_PORTB

Enable Port B.

CONFIG_GPIO_GECKO_PORTC

Enable Port C.

CONFIG_GPIO_GECKO_PORTD

Enable Port D.

CONFIG_GPIO_GECKO_PORTE

Enable Port E.

CONFIG_GPIO_GECKO_PORTF

Enable Port F.

CONFIG_GPIO_GECKO_PORTG

Enable Port G.

CONFIG_GPIO_GECKO_PORTH

Enable Port H.

CONFIG_GPIO_GECKO_PORTI

Enable Port I.

CONFIG_GPIO_GECKO_PORTJ

Enable Port J.

CONFIG_GPIO_GECKO_PORTK

Enable Port K.

CONFIG_GPIO_G_STELLARIS

Enable GPIO port G support

CONFIG_GPIO_HT16K33

Enable keyscan driver for HT16K33.

The HT16K33 is a memory mapping, multifunction LED controller driver. The controller supports matrix key scan circuit of up to 13x3 keys.

The keyscan functionality is exposed as up to 3 GPIO controller drivers, each supporting GPIO callbacks for keyscan event notifications.

CONFIG_GPIO_HT16K33_INIT_PRIORITY

Device driver initialization priority. This driver must be initialized after the HT16K33 LED driver.

CONFIG_GPIO_IMX

Enable the IMX GPIO driver.

CONFIG_GPIO_IMX_PORT_1

Enable Port 1.

CONFIG_GPIO_IMX_PORT_2

Enable Port 2.

CONFIG_GPIO_IMX_PORT_3

Enable Port 3.

CONFIG_GPIO_IMX_PORT_4

Enable Port 4.

CONFIG_GPIO_IMX_PORT_5

Enable Port 5.

CONFIG_GPIO_IMX_PORT_6

Enable Port 6.

CONFIG_GPIO_IMX_PORT_7

Enable Port 7.

CONFIG_GPIO_INTEL_APL

Enable driver for Intel Apollo Lake SoC GPIO

CONFIG_GPIO_INTEL_APL_CHECK_PERMS

This option enables the checks to make sure the GPIO pin can be manipulated. Only if the pin is owned by the host software and its functioning as GPIO, then the driver allows manipulating the pin.

Say y if unsure.

CONFIG_GPIO_LMP90XXX

Enable GPIO driver for LMP90xxx.

The LMP90xxx is a multi-channel, low power sensor analog frontend (AFE).

The GPIO port of the LMP90xxx (D6 to D0) is exposed as a GPIO controller driver with read/write support.

CONFIG_GPIO_LMP90XXX_INIT_PRIORITY

Device driver initialization priority. This driver must be initialized after the LMP90xxx ADC driver.

CONFIG_GPIO_MCUX

Enable the MCUX pinmux driver.

CONFIG_GPIO_MCUX_IGPIO

Enable the MCUX IGPIO driver.

CONFIG_GPIO_MCUX_IGPIO_1

Enable Port 1.

CONFIG_GPIO_MCUX_IGPIO_2

Enable Port 2.

CONFIG_GPIO_MCUX_IGPIO_3

Enable Port 3.

CONFIG_GPIO_MCUX_IGPIO_4

Enable Port 4.

CONFIG_GPIO_MCUX_IGPIO_5

Enable Port 5.

CONFIG_GPIO_MCUX_LPC

Enable the MCUX LPC pinmux driver.

CONFIG_GPIO_MCUX_LPC_PORT0

Enable Port 0.

CONFIG_GPIO_MCUX_LPC_PORT0_NAME

Port 0 driver name

CONFIG_GPIO_MCUX_LPC_PORT1

Enable Port 1.

CONFIG_GPIO_MCUX_LPC_PORT1_NAME

Port 1 driver name

CONFIG_GPIO_MCUX_PORTA

Enable Port A.

CONFIG_GPIO_MCUX_PORTB

Enable Port B.

CONFIG_GPIO_MCUX_PORTC

Enable Port C.

CONFIG_GPIO_MCUX_PORTD

Enable Port D.

CONFIG_GPIO_MCUX_PORTE

Enable Port E.

CONFIG_GPIO_MMIO32

This is a driver for accessing a simple, fixed purpose, 32-bit memory-mapped i/o register using the same APIs as GPIO drivers. This is useful when an SoC or board has registers that aren’t part of a GPIO IP block and these registers are used to control things that Zephyr normally expects to be specified using a GPIO pin, e.g. for driving an LED, or chip-select line for an SPI device.

CONFIG_GPIO_NRFX

Enable GPIO driver for nRF line of MCUs.

CONFIG_GPIO_NRF_INIT_PRIORITY

Initialization priority for nRF GPIO.

CONFIG_GPIO_NRF_P0

Enable nRF GPIO port P0 config options.

CONFIG_GPIO_NRF_P1

Enable nRF GPIO port P1 config options.

CONFIG_GPIO_PCAL9535A

Enable driver for PCAL9535A I2C-based GPIO chip.

CONFIG_GPIO_PCAL9535A_0

Enable config options for the PCAL9535A I2C-based GPIO chip #0.

CONFIG_GPIO_PCAL9535A_0_DEV_NAME

Specify the device name for the PCAL9535A I2C-based GPIO chip #0.

CONFIG_GPIO_PCAL9535A_0_I2C_ADDR

Specify the I2C slave address for the PCAL9535A I2C-based GPIO chip #0.

CONFIG_GPIO_PCAL9535A_0_I2C_MASTER_DEV_NAME

Specify the device name of the I2C master device to which this PCAL9535A chip #0 is binded.

CONFIG_GPIO_PCAL9535A_1

Enable config options for the PCAL9535A I2C-based GPIO chip #1.

CONFIG_GPIO_PCAL9535A_1_DEV_NAME

Specify the device name for the PCAL9535A I2C-based GPIO chip #1.

CONFIG_GPIO_PCAL9535A_1_I2C_ADDR

Specify the I2C slave address for the PCAL9535A I2C-based GPIO chip #1.

CONFIG_GPIO_PCAL9535A_1_I2C_MASTER_DEV_NAME

Specify the device name of the I2C master device to which this PCAL9535A chip #1 is binded.

CONFIG_GPIO_PCAL9535A_2

Enable config options for the PCAL9535A I2C-based GPIO chip #2.

CONFIG_GPIO_PCAL9535A_2_DEV_NAME

Specify the device name for the PCAL9535A I2C-based GPIO chip #2.

CONFIG_GPIO_PCAL9535A_2_I2C_ADDR

Specify the I2C slave address for the PCAL9535A I2C-based GPIO chip #2.

CONFIG_GPIO_PCAL9535A_2_I2C_MASTER_DEV_NAME

Specify the device name of the I2C master device to which this PCAL9535A chip #2 is binded.

CONFIG_GPIO_PCAL9535A_3

Enable config options for the PCAL9535A I2C-based GPIO chip #3.

CONFIG_GPIO_PCAL9535A_3_DEV_NAME

Specify the device name for the PCAL9535A I2C-based GPIO chip #3.

CONFIG_GPIO_PCAL9535A_3_I2C_ADDR

Specify the I2C slave address for the PCAL9535A I2C-based GPIO chip #3.

CONFIG_GPIO_PCAL9535A_3_I2C_MASTER_DEV_NAME

Specify the device name of the I2C master device to which this PCAL9535A chip #3 is binded.

CONFIG_GPIO_PCAL9535A_INIT_PRIORITY

Device driver initialization priority.

CONFIG_GPIO_RV32M1

Enable the RV32M1 GPIO driver.

CONFIG_GPIO_RV32M1_PORTA

Enable Port A.

CONFIG_GPIO_RV32M1_PORTB

Enable Port B.

CONFIG_GPIO_RV32M1_PORTC

Enable Port C.

CONFIG_GPIO_RV32M1_PORTD

Enable Port D.

CONFIG_GPIO_RV32M1_PORTE

Enable Port E.

CONFIG_GPIO_SAM

Enable support for the Atmel SAM ‘PORT’ GPIO controllers.

CONFIG_GPIO_SAM0

Enable support for the Atmel SAM0 ‘PORT’ GPIO controllers.

CONFIG_GPIO_SHELL

Enable GPIO Shell for testing.

CONFIG_GPIO_SIFIVE

Enable driver for the SiFive Freedom GPIO controller.

Says n if not sure.

CONFIG_GPIO_SIFIVE_0_PRIORITY

GPIO 0 interrupt priority

CONFIG_GPIO_SIFIVE_10_PRIORITY

GPIO 10 interrupt priority

CONFIG_GPIO_SIFIVE_11_PRIORITY

GPIO 11 interrupt priority

CONFIG_GPIO_SIFIVE_12_PRIORITY

GPIO 12 interrupt priority

CONFIG_GPIO_SIFIVE_13_PRIORITY

GPIO 13 interrupt priority

CONFIG_GPIO_SIFIVE_14_PRIORITY

GPIO 14 interrupt priority

CONFIG_GPIO_SIFIVE_15_PRIORITY

GPIO 15 interrupt priority

CONFIG_GPIO_SIFIVE_16_PRIORITY

GPIO 16 interrupt priority

CONFIG_GPIO_SIFIVE_17_PRIORITY

GPIO 17 interrupt priority

CONFIG_GPIO_SIFIVE_18_PRIORITY

GPIO 18 interrupt priority

CONFIG_GPIO_SIFIVE_19_PRIORITY

GPIO 19 interrupt priority

CONFIG_GPIO_SIFIVE_1_PRIORITY

GPIO 1 interrupt priority

CONFIG_GPIO_SIFIVE_20_PRIORITY

GPIO 20 interrupt priority

CONFIG_GPIO_SIFIVE_21_PRIORITY

GPIO 21 interrupt priority

CONFIG_GPIO_SIFIVE_22_PRIORITY

GPIO 22 interrupt priority

CONFIG_GPIO_SIFIVE_23_PRIORITY

GPIO 23 interrupt priority

CONFIG_GPIO_SIFIVE_24_PRIORITY

GPIO 24 interrupt priority

CONFIG_GPIO_SIFIVE_25_PRIORITY

GPIO 25 interrupt priority

CONFIG_GPIO_SIFIVE_26_PRIORITY

GPIO 26 interrupt priority

CONFIG_GPIO_SIFIVE_27_PRIORITY

GPIO 27 interrupt priority

CONFIG_GPIO_SIFIVE_28_PRIORITY

GPIO 28 interrupt priority

CONFIG_GPIO_SIFIVE_29_PRIORITY

GPIO 29 interrupt priority

CONFIG_GPIO_SIFIVE_2_PRIORITY

GPIO 2 interrupt priority

CONFIG_GPIO_SIFIVE_30_PRIORITY

GPIO 30 interrupt priority

CONFIG_GPIO_SIFIVE_31_PRIORITY

GPIO 31 interrupt priority

CONFIG_GPIO_SIFIVE_3_PRIORITY

GPIO 3 interrupt priority

CONFIG_GPIO_SIFIVE_4_PRIORITY

GPIO 4 interrupt priority

CONFIG_GPIO_SIFIVE_5_PRIORITY

GPIO 5 interrupt priority

CONFIG_GPIO_SIFIVE_6_PRIORITY

GPIO 6 interrupt priority

CONFIG_GPIO_SIFIVE_7_PRIORITY

GPIO 7 interrupt priority

CONFIG_GPIO_SIFIVE_8_PRIORITY

GPIO 8 interrupt priority

CONFIG_GPIO_SIFIVE_9_PRIORITY

GPIO 9 interrupt priority

CONFIG_GPIO_STELLARIS

Enable support for the Stellaris GPIO controllers.

CONFIG_GPIO_STM32

Enable GPIO driver for STM32 line of MCUs

CONFIG_GPIO_STM32_PORTA

Enable GPIO port A support

CONFIG_GPIO_STM32_PORTB

Enable GPIO port B support

CONFIG_GPIO_STM32_PORTC

Enable GPIO port C support

CONFIG_GPIO_STM32_PORTD

Enable GPIO port D support

CONFIG_GPIO_STM32_PORTE

Enable GPIO port E support

CONFIG_GPIO_STM32_PORTF

Enable GPIO port F support

CONFIG_GPIO_STM32_PORTG

Enable GPIO port G support

CONFIG_GPIO_STM32_PORTH

Enable GPIO port H support

CONFIG_GPIO_STM32_PORTI

Enable GPIO port I support

CONFIG_GPIO_STM32_PORTJ

Enable GPIO port J support

CONFIG_GPIO_STM32_PORTK

Enable GPIO port K support

CONFIG_GPIO_STM32_SWJ_DISABLE

JTAG-DP Disabled and SW-DP Disabled

CONFIG_GPIO_STM32_SWJ_ENABLE

Full SWJ (JTAG-DP + SW-DP): Reset State

CONFIG_GPIO_STM32_SWJ_NOJTAG

JTAG-DP Disabled and SW-DP Enabled

CONFIG_GPIO_STM32_SWJ_NONJTRST

Full SWJ (JTAG-DP + SW-DP) but without NJTRST

CONFIG_GPIO_SX1509B

Enable driver for SX1509B I2C GPIO chip.

CONFIG_GPIO_SX1509B_INIT_PRIORITY

Device driver initialization priority.

CONFIG_GPIO_XEC

Enable the Microchip XEC gpio driver.

CONFIG_GPIO_XEC_GPIO000_036

Enable GPIO 000-036 or what would be equivalent to PortA.

CONFIG_GPIO_XEC_GPIO040_076

Enable GPIO 040-076 or what would be equivalent to Port B

CONFIG_GPIO_XEC_GPIO100_136

Enable GPIO 100-136 or what would be equivalent to Port C

CONFIG_GPIO_XEC_GPIO140_176

Enable GPIO 140-176 or what would be equivalent to Port C

CONFIG_GPIO_XEC_GPIO200_236

Enable GPIO 200-236 or what would be equivalent to Port D

CONFIG_GPIO_XEC_GPIO240_276

Enable GPIO 240-276 or what would be equivalent to Port E

CONFIG_GROVE_LCD_RGB

Setting this value will enable driver support for the Groove-LCD RGB Backlight.

CONFIG_GROVE_LCD_RGB_I2C_MASTER_DEV_NAME

Specify the device name of the I2C master device to which the Grove LCD is connected.

CONFIG_GROVE_LIGHT_SENSOR

Setting this value will enable driver support for the Grove Light Sensor.

CONFIG_GROVE_LIGHT_SENSOR_ADC_CHANNEL

Specify the channel of the ADC to which the Grove Light Sensor is connected.

CONFIG_GROVE_LIGHT_SENSOR_ADC_DEV_NAME

Specify the device name of the ADC to which the Grove Light Sensor is connected.

CONFIG_GROVE_LIGHT_SENSOR_NAME

Specify the device name with which the sensor is identified.

CONFIG_GROVE_TEMPERATURE_SENSOR

Setting this value will enable driver support for the Grove Temperature Sensor.

CONFIG_GROVE_TEMPERATURE_SENSOR_ADC_CHANNEL

Specify the channel of the ADC to which the Grove Temperature Sensor is connected.

CONFIG_GROVE_TEMPERATURE_SENSOR_ADC_DEV_NAME

Specify the device name of the ADC to which the Grove Temperature Sensor is connected.

CONFIG_GROVE_TEMPERATURE_SENSOR_NAME

Specify the device name with which the Grove Temperature Sensor is identified.

CONFIG_GROVE_TEMPERATURE_SENSOR_V1_0

Version 1.0

CONFIG_GROVE_TEMPERATURE_SENSOR_V1_X

Version 1.1 or 1.2

CONFIG_HAS_I2C_DW

CONFIG_HAS_SPI_DW

Signifies whether DesignWare SPI compatible HW is available

CONFIG_HAS_WDT_MULTISTAGE

CONFIG_HMC5883L

Enable driver for HMC5883L I2C-based magnetometer.

CONFIG_HMC5883L_FS

Magnetometer full-scale range. An X value for the config represents a range of +/- X gauss. Valid values are 0.88, 1.3, 1.9, 2.5, 4, 4.7, 5.6 and 8.1.

CONFIG_HMC5883L_ODR

Magnetometer output data rate expressed in samples per second. Data rates supported by the chip are 0.75, 1.5, 3, 7.5, 15, 30 and 75.

CONFIG_HMC5883L_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_HMC5883L_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_HMC5883L_TRIGGER

CONFIG_HMC5883L_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_HMC5883L_TRIGGER_NONE

No trigger

CONFIG_HMC5883L_TRIGGER_OWN_THREAD

Use own thread

CONFIG_HP206C

Enable HopeRF HP206C barometer and altimeter support.

CONFIG_HP206C_ALT_OFFSET

Value, in cm, that will be used to compensate altitude calculation. For more info on how to choose this value, consult section 6.1.1 in the datasheet.

CONFIG_HP206C_ALT_OFFSET_RUNTIME

Altitude offset set at runtime

CONFIG_HP206C_OSR

Allowed values: 4096, 2048, 1024, 512, 256, 128

CONFIG_HP206C_OSR_RUNTIME

Oversampling rate set at runtime

CONFIG_HPET_TIMER

This option selects High Precision Event Timer (HPET) as a system timer.

CONFIG_HT16K33

Enable LED driver for HT16K33.

The HT16K33 is a memory mapping, multifunction LED controller driver. The controller supports up to 128 LEDs (up to 16 rows and 8 commons).

CONFIG_HT16K33_KEYSCAN

Enable keyscan child device support in the HT16K33 LED driver.

The keyscan functionality itself is handled by the HT16K33 GPIO driver.

CONFIG_HT16K33_KEYSCAN_DEBOUNCE_MSEC

Keyscan debounce interval in milliseconds.

CONFIG_HT16K33_KEYSCAN_IRQ_THREAD_PRIO

Priority level for internal thread for keyscan interrupt processing.

CONFIG_HT16K33_KEYSCAN_IRQ_THREAD_STACK_SIZE

Size of the stack used for internal thread for keyscan interrupt processing.

CONFIG_HT16K33_KEYSCAN_POLL_MSEC

Keyscan poll interval in milliseconds. Polling is only used if no interrupt line is present.

CONFIG_HTS221

Enable driver for HTS221 I2C-based temperature and humidity sensor.

CONFIG_HTS221_ODR

Sensor output data rate expressed in samples per second. Data rates supported by the chip are 1, 7 and 12.5.

CONFIG_HTS221_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_HTS221_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_HTS221_TRIGGER

CONFIG_HTS221_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_HTS221_TRIGGER_NONE

No trigger

CONFIG_HTS221_TRIGGER_OWN_THREAD

Use own thread

CONFIG_HWINFO

Enable hwinfo driver.

CONFIG_HWINFO_ESP32

Enable ESP32 hwinfo driver.

CONFIG_HWINFO_IMXRT

Enable NXP i.mx RT hwinfo driver.

CONFIG_HWINFO_LITEX

Enable LiteX hwinfo driver

CONFIG_HWINFO_MCUX_SIM

Enable NXP kinetis mcux hwinfo driver.

CONFIG_HWINFO_NRF

Enable Nordic NRF hwinfo driver.

CONFIG_HWINFO_SAM

Enable Atmel SAM hwinfo driver.

CONFIG_HWINFO_SAM0

Enable Atmel SAM0 hwinfo driver.

CONFIG_HWINFO_SHELL

Enable hwinfo Shell for testing.

CONFIG_HWINFO_STM32

Enable STM32 hwinfo driver.

CONFIG_I2C

Enable I2C Driver Configuration

CONFIG_I2C_0

Enable I2C Port 0

CONFIG_I2C_0_IRQ_PRI

IRQ priority.

CONFIG_I2C_0_NRF_TWI

Enable nRF TWI Master without EasyDMA on port 0.

CONFIG_I2C_0_NRF_TWIM

Enable nRF TWI Master with EasyDMA on port 0. This peripheral accepts transfers from RAM only, if provided buffer is placed in flash, transfer will fail.

CONFIG_I2C_1

Enable I2C Port 1

CONFIG_I2C_1_NRF_TWI

Enable nRF TWI Master without EasyDMA on port 1.

CONFIG_I2C_1_NRF_TWIM

Enable nRF TWI Master with EasyDMA on port 1. This peripheral accepts transfers from RAM only, if provided buffer is placed in flash, transfer will fail.

CONFIG_I2C_2

Enable I2C Port 2

CONFIG_I2C_2_NRF_TWIM

Enable nRF TWI Master with EasyDMA on port 2. This peripheral accepts transfers from RAM only, if provided buffer is placed in flash, transfer will fail.

CONFIG_I2C_3

Enable I2C Port 3

CONFIG_I2C_3_NRF_TWIM

Enable nRF TWI Master with EasyDMA on port 3. This peripheral accepts transfers from RAM only, if provided buffer is placed in flash, transfer will fail.

CONFIG_I2C_4

Enable I2C Port 4

CONFIG_I2C_5

Enable I2C Port 5

CONFIG_I2C_6

Enable I2C Port 6

CONFIG_I2C_7

Enable I2C Port 7

CONFIG_I2C_BITBANG

Enable library used for software driven (bit banging) I2C support

CONFIG_I2C_CC13XX_CC26XX

Enable support for I2C on the TI SimpleLink CC13xx / CC26xx series.

CONFIG_I2C_CC32XX

Enable the CC32XX I2C driver.

CONFIG_I2C_DW

Enable the Design Ware I2C driver

CONFIG_I2C_DW_CLOCK_SPEED

Set the clock speed for I2C

CONFIG_I2C_EEPROM_SLAVE

Enable virtual I2C Slave EEPROM driver

CONFIG_I2C_ESP32

Enables the ESP32 I2C driver

CONFIG_I2C_ESP32_0_IRQ

Port 0 IRQ line

CONFIG_I2C_ESP32_0_RX_LSB_FIRST

Port 0 Receive LSB first

CONFIG_I2C_ESP32_0_TX_LSB_FIRST

Port 0 Transmit LSB first

CONFIG_I2C_ESP32_1_IRQ

Port 1 IRQ line

CONFIG_I2C_ESP32_1_RX_LSB_FIRST

Port 1 Receive LSB first

CONFIG_I2C_ESP32_1_TX_LSB_FIRST

Port 1 Transmit LSB first

CONFIG_I2C_ESP32_TIMEOUT

I2C timeout to receive a data bit in APB clock cycles

CONFIG_I2C_GECKO

Enable the SiLabs Gecko I2C bus driver.

CONFIG_I2C_GPIO

Enable software driven (bit banging) I2C support using GPIO pins

CONFIG_I2C_GPIO_0

This tells the driver to configure the I2C device at boot, depending on the additional configuration options below.

CONFIG_I2C_GPIO_0_GPIO

This is the name of the GPIO device that controls the I2C lines.

CONFIG_I2C_GPIO_0_NAME

This is the device name for the I2C device, and is included in the device struct.

CONFIG_I2C_GPIO_0_SCL_PIN

This is the GPIO pin number for the I2S SCL line

CONFIG_I2C_GPIO_0_SDA_PIN

This is the GPIO pin number for the I2S SDA line

CONFIG_I2C_GPIO_1

This tells the driver to configure the I2C device at boot, depending on the additional configuration options below.

CONFIG_I2C_GPIO_1_GPIO

This is the name of the GPIO device that controls the I2C lines.

CONFIG_I2C_GPIO_1_NAME

This is the device name for the I2C device, and is included in the device struct.

CONFIG_I2C_GPIO_1_SCL_PIN

This is the GPIO pin number for the I2S SCL line

CONFIG_I2C_GPIO_1_SDA_PIN

This is the GPIO pin number for the I2S SDA line

CONFIG_I2C_GPIO_2

This tells the driver to configure the I2C device at boot, depending on the additional configuration options below.

CONFIG_I2C_GPIO_2_GPIO

This is the name of the GPIO device that controls the I2C lines.

CONFIG_I2C_GPIO_2_NAME

This is the device name for the I2C device, and is included in the device struct.

CONFIG_I2C_GPIO_2_SCL_PIN

This is the GPIO pin number for the I2S SCL line

CONFIG_I2C_GPIO_2_SDA_PIN

This is the GPIO pin number for the I2S SDA line

CONFIG_I2C_GPIO_3

This tells the driver to configure the I2C device at boot, depending on the additional configuration options below.

CONFIG_I2C_GPIO_3_GPIO

This is the name of the GPIO device that controls the I2C lines.

CONFIG_I2C_GPIO_3_NAME

This is the device name for the I2C device, and is included in the device struct.

CONFIG_I2C_GPIO_3_SCL_PIN

This is the GPIO pin number for the I2C SCL line

CONFIG_I2C_GPIO_3_SDA_PIN

This is the GPIO pin number for the I2C SDA line

CONFIG_I2C_IMX

Enable the i.MX I2C driver.

CONFIG_I2C_INIT_PRIORITY

I2C device driver initialization priority.

CONFIG_I2C_LITEX

Enable support for Litex I2C driver

CONFIG_I2C_MCUX

Enable the mcux I2C driver.

CONFIG_I2C_MCUX_LPI2C

Enable the mcux LPI2C driver.

CONFIG_I2C_NIOS2

Enable the Nios-II I2C driver.

CONFIG_I2C_NRFX

Enable support for nrfx TWI drivers for nRF MCU series. Peripherals with the same instance ID cannot be used together, e.g. I2C_0 and SPI_0. You may need to disable SPI_0 or SPI_1.

CONFIG_I2C_RV32M1_LPI2C

Enable the RV32M1 LPI2C driver.

CONFIG_I2C_SAM0

Enable the SAM0 series SERCOM I2C driver.

CONFIG_I2C_SAM0_DMA_DRIVEN

This enables DMA driven transactions for the I2C peripheral. DMA driven mode requires fewer interrupts to handle the transaction and ensures that high speed modes are not delayed by data reloading.

CONFIG_I2C_SAM_TWI

Enable Atmel SAM MCU Family (TWI) I2C bus driver.

CONFIG_I2C_SAM_TWIHS

Enable Atmel SAM MCU Family (TWIHS) I2C bus driver.

CONFIG_I2C_SBCON

I2C driver for ARM’s SBCon two-wire serial bus interface

CONFIG_I2C_SHELL

Enable I2C Shell.

The I2C shell currently support scanning.

CONFIG_I2C_SIFIVE

Enable I2C support on SiFive Freedom

CONFIG_I2C_SLAVE

Enable I2C Slave Driver Configuration

CONFIG_I2C_SLAVE_INIT_PRIORITY

I2C Slave device driver initialization priority.

CONFIG_I2C_STM32

Enable I2C support on the STM32 SoCs

CONFIG_I2C_STM32_COMBINED_INTERRUPT

CONFIG_I2C_STM32_INTERRUPT

Enable Interrupt support for the I2C Driver

CONFIG_I2C_STM32_V1

Enable I2C support on the STM32 F1 and F4X family of processors. This driver also supports the F2 and L1 series.

CONFIG_I2C_STM32_V2

Enable I2C support on the STM32 F0, F3, F7, L4, WBX, MP1, G0 and G4 family of processors. This driver also supports the L0 series. If I2C_SLAVE is enabled it selects I2C_STM32_INTERRUPT, since slave mode is only supported by this driver with interrupts enabled.

CONFIG_I2C_XEC

Enable the Microchip XEC I2C driver.

CONFIG_I2S

Enable support for the I2S (Inter-IC Sound) hardware bus.

CONFIG_I2S_1

Enable I2S controller port 1.

CONFIG_I2S_2

Enable I2S controller port 2.

CONFIG_I2S_3

Enable I2S controller port 3.

CONFIG_I2S_4

Enable I2S controller port 4.

CONFIG_I2S_5

Enable I2S controller port 5.

CONFIG_I2S_CAVS

Enable Inter Sound (I2S) bus driver for Intel_S1000 based on Synchronous Serial Port (SSP) module.

CONFIG_I2S_CAVS_1_DMA_RX_CHANNEL

DMA channel number to use for I2S1 RX transfer.

CONFIG_I2S_CAVS_1_DMA_TX_CHANNEL

DMA channel number to use for I2S1 TX transfer.

CONFIG_I2S_CAVS_1_NAME

I2S 1 device name

CONFIG_I2S_CAVS_2_DMA_RX_CHANNEL

DMA channel number to use for I2S2 RX transfer.

CONFIG_I2S_CAVS_2_DMA_TX_CHANNEL

DMA channel number to use for I2S2 TX transfer.

CONFIG_I2S_CAVS_2_NAME

I2S 2 device name

CONFIG_I2S_CAVS_3_DMA_RX_CHANNEL

DMA channel number to use for I2S3 RX transfer.

CONFIG_I2S_CAVS_3_DMA_TX_CHANNEL

DMA channel number to use for I2S3 TX transfer.

CONFIG_I2S_CAVS_3_NAME

I2S 3 device name

CONFIG_I2S_CAVS_DMA_NAME

Name of the DMA device this device driver can use.

CONFIG_I2S_CAVS_IRQ_PRI

Interrupt priority

CONFIG_I2S_INIT_PRIORITY

Device driver initialization priority.

CONFIG_I2S_SAM_SSC

Enable Inter Sound (I2S) bus driver for Atmel SAM MCU family based on Synchronous Serial Controller (SSC) module.

CONFIG_I2S_SAM_SSC_0_DMA_RX_CHANNEL

DMA channel number to use for RX transfers.

CONFIG_I2S_SAM_SSC_0_DMA_TX_CHANNEL

DMA channel number to use for TX transfers.

CONFIG_I2S_SAM_SSC_0_IRQ_PRI

Interrupt priority

CONFIG_I2S_SAM_SSC_0_NAME

I2S 0 device name

CONFIG_I2S_SAM_SSC_0_PIN_RF_EN

If enabled RF signal is connected to RF pin. It will be configured as an output or an input depending on whether the receiver is working in master or slave mode.

If disabled RF signal is disconnected from RF pin and connected internally to TF (Transmitter Frame Synchro signal).

CONFIG_I2S_SAM_SSC_0_PIN_RK_EN

If enabled RK signal is connected to RK pin. It will be configured as an output or an input depending on whether the receiver is working in master or slave mode.

If disabled RK signal is disconnected from RK pin and connected internally to TK (Transmitter Clock signal).

CONFIG_I2S_SAM_SSC_0_PIN_TD_PB5

PB5

CONFIG_I2S_SAM_SSC_0_PIN_TD_PD10

PD10

CONFIG_I2S_SAM_SSC_0_PIN_TD_PD26

PD26

CONFIG_I2S_SAM_SSC_DMA_NAME

Name of the DMA device this device driver can use.

CONFIG_I2S_SAM_SSC_RX_BLOCK_COUNT

RX queue length

CONFIG_I2S_SAM_SSC_TX_BLOCK_COUNT

TX queue length

CONFIG_I2S_STM32

Enable I2S support on the STM32 family of processors. (Tested on the STM32F4 series)

CONFIG_I2S_STM32_PLLI2S_PLLM

Division factor for the audio PLL (PLLI2S) VCO input clock. PLLM factor should be selected to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter. Allowed values: 2-63

CONFIG_I2S_STM32_PLLI2S_PLLN

Multiply factor for the audio PLL (PLLI2S) VCO output clock. PLLN factor should be selected to ensure that the VCO output frequency ranges from 100 to 432 MHz. Allowed values: 50-432

CONFIG_I2S_STM32_PLLI2S_PLLR

Division factor for the I2S clock. PLLR factor should be selected to ensure that the I2S clock frequency is less than or equal to 192MHz. Allowed values: 2-7

CONFIG_I2S_STM32_RX_BLOCK_COUNT

RX queue length

CONFIG_I2S_STM32_TX_BLOCK_COUNT

TX queue length

CONFIG_I2S_STM32_USE_PLLI2S_ENABLE

Enable it if I2S clock should be provided by the PLLI2S. If not enabled the clock will be provided by HSI/HSE.

CONFIG_IAQ_CORE_MAX_READ_RETRIES

Number of retries when reading failed or device not ready.

CONFIG_IEEE802154

IEEE 802.15.4 drivers options

CONFIG_IEEE802154_CC1200

TI CC1200 Driver support

CONFIG_IEEE802154_CC1200_CCA_THRESHOLD

Set the CCA threshold. See datasheet’s AGC_CS_THR register for more information. Do not touch this unless you know what you are doing.

CONFIG_IEEE802154_CC1200_DRV_NAME

This option sets the driver name

CONFIG_IEEE802154_CC1200_GPIO_SPI_CS

This option is useful if one needs to manage SPI CS through a GPIO pin to by-pass the SPI controller’s CS logic.

CONFIG_IEEE802154_CC1200_INIT_PRIO

Set the initialization priority number. Do not mess with it unless you know what you are doing. Beware cc1200 requires gpio and spi to be ready first (and sometime gpio should be the very first as spi might need it too). And of course it has to start before the net stack.

CONFIG_IEEE802154_CC1200_MAC4

This is the byte 4 of the MAC address.

CONFIG_IEEE802154_CC1200_MAC5

This is the byte 5 of the MAC address.

CONFIG_IEEE802154_CC1200_MAC6

This is the byte 6 of the MAC address.

CONFIG_IEEE802154_CC1200_MAC7

This is the byte 7 of the MAC address.

CONFIG_IEEE802154_CC1200_PKTCFG0

CONFIG_IEEE802154_CC1200_PKTCFG1

CONFIG_IEEE802154_CC1200_PKTCFG2

CONFIG_IEEE802154_CC1200_RANDOM_MAC

Generate a random MAC address dynamically.

CONFIG_IEEE802154_CC1200_RFEND_CFG0

CONFIG_IEEE802154_CC1200_RFEND_CFG1

CONFIG_IEEE802154_CC1200_RF_PRESET

Use TI CC1200 RF pre-sets

CONFIG_IEEE802154_CC1200_RF_SET_0

868MHz - 50Kbps - 2-GFSK - IEEE 802.15.4g compliant - ETSI

CONFIG_IEEE802154_CC1200_RF_SET_1

920MHz - 50Kbps - 2-GFSK - IEEE 802.15.4g compliant - ARIB

CONFIG_IEEE802154_CC1200_RF_SET_2

434MHz - 50Kbps - 2-GFSK - IEEE 802.15.4g compliant - ETSI

CONFIG_IEEE802154_CC1200_RSSI_OFFSET

Set the gain adjustment. See datasheet’s AGC_GAIN_ADJUST register for more information. Do not touch this unless you know what you are doing.

CONFIG_IEEE802154_CC1200_RX_STACK_SIZE

This option sets the driver’s stack size for its internal RX thread. The default value should be sufficient, but in case it proves to be a too little one, this option makes it easy to play with the size.

CONFIG_IEEE802154_CC1200_SETTLING_CFG

CONFIG_IEEE802154_CC1200_XOSC

This sets the XOSC value, it must be between 38400 and 40000. This value should follow what has been set in the RF settings via SmartRF tool. Do not touch this unless you know what you are doing.

CONFIG_IEEE802154_CC13XX_CC26XX

TI CC13xx / CC26xx IEEE 802.15.4 driver support

CONFIG_IEEE802154_CC13XX_CC26XX_DRV_NAME

This option sets the driver name.

CONFIG_IEEE802154_CC13XX_CC26XX_INIT_PRIO

Set the initialization priority number.

CONFIG_IEEE802154_CC13XX_CC26XX_RX_STACK_SIZE

This option sets the driver’s stack size for its internal RX thread.

CONFIG_IEEE802154_CC2520

TI CC2520 Driver support

CONFIG_IEEE802154_CC2520_CRYPTO

This option will expose the hardware AES encryption from CC2520. Such feature should not be used for anything but 802.15.4 security. The crypto device exposed will only support synchronous CCM operation.

CONFIG_IEEE802154_CC2520_CRYPTO_DRV_NAME

This option sets the driver name for the crypto part found on CC2520.

CONFIG_IEEE802154_CC2520_CRYPTO_INIT_PRIO

Set the initialization priority number. Do not mess with it unless you know what you are doing. It should be initialized after CC2520 as it shares the same runtime context.

CONFIG_IEEE802154_CC2520_DRV_NAME

This option sets the driver name

CONFIG_IEEE802154_CC2520_GPIO_SPI_CS

This option is useful if one needs to manage SPI CS through a GPIO pin to by-pass the SPI controller’s CS logic.

CONFIG_IEEE802154_CC2520_INIT_PRIO

Set the initialization priority number. Do not mess with it unless you know what you are doing. Beware cc2520 requires gpio and spi to be ready first (and sometime gpio should be the very first as spi might need it too). And of course it has to start before the net stack.

CONFIG_IEEE802154_CC2520_MAC4

This is the byte 4 of the MAC address.

CONFIG_IEEE802154_CC2520_MAC5

This is the byte 5 of the MAC address.

CONFIG_IEEE802154_CC2520_MAC6

This is the byte 6 of the MAC address.

CONFIG_IEEE802154_CC2520_MAC7

This is the byte 7 of the MAC address.

CONFIG_IEEE802154_CC2520_RANDOM_MAC

Generate a random MAC address dynamically.

CONFIG_IEEE802154_CC2520_RX_STACK_SIZE

This option sets the driver’s stack size for its internal RX thread. The default value should be sufficient, but in case it proves to be a too little one, this option makes it easy to play with the size.

CONFIG_IEEE802154_KW41Z

NXP KW41Z Driver support

CONFIG_IEEE802154_KW41Z_DRV_NAME

This option sets the driver name. Do not change it unless you know what you are doing.

CONFIG_IEEE802154_KW41Z_INIT_PRIO

Set the initialization priority number. Do not change it unless you know what you are doing. It has to start before the net stack.

CONFIG_IEEE802154_MCR20A

NXP MCR20A Driver support

CONFIG_IEEE802154_MCR20A_DRV_NAME

This option sets the driver name

CONFIG_IEEE802154_MCR20A_INIT_PRIO

Set the initialization priority number. Do not mess with it unless you know what you are doing. Beware mcr20a requires gpio and spi to be ready first (and sometime gpio should be the very first as spi might need it too). And of course it has to start before the net stack.

CONFIG_IEEE802154_MCR20A_RX_STACK_SIZE

This option sets the driver’s stack size for its internal RX thread. The default value should be sufficient, but in case it proves to be a too little one, this option makes it easy to play with the size.

CONFIG_IEEE802154_NRF5

nRF52 series IEEE 802.15.4 Driver

CONFIG_IEEE802154_NRF5_DRV_NAME

This option sets the driver name

CONFIG_IEEE802154_NRF5_INIT_PRIO

Set the initialization priority number. Do not mess with it unless you know what you are doing.

CONFIG_IEEE802154_NRF5_RX_STACK_SIZE

This option sets the driver’s stack size for its internal RX thread. The default value should be sufficient, but in case it proves to be a too little one, this option makes it easy to play with the size.

CONFIG_IEEE802154_RAW_MODE

This option enables using the drivers in a so-called “raw” mode, i.e. without a MAC stack (the net L2 layer for 802.15.4 will not be built). Used only for very specific cases, such as wpan_serial and wpanusb samples.

CONFIG_IEEE802154_RF2XX

ATMEL RF2XX Driver support

CONFIG_IEEE802154_RF2XX_DRV_NAME

This option sets the driver name

CONFIG_IEEE802154_RF2XX_INIT_PRIO

Set the initialization priority number. Do not mess with it unless you know what you are doing. Beware rf2xx requires gpio and spi to be ready first (and sometime gpio should be the very first as spi might need it too). And of course it has to start before the net stack.

CONFIG_IEEE802154_RF2XX_RX_STACK_SIZE

This option sets the driver’s stack size for its internal RX thread. The default value should be sufficient, but in case it proves to be a too little one, this option makes it easy to play with the size.

CONFIG_IEEE802154_UPIPE

UART PIPE fake radio driver support for QEMU

CONFIG_IEEE802154_UPIPE_DRV_NAME

UART PIPE Driver name

CONFIG_IEEE802154_UPIPE_HW_FILTER

This option assure the driver will process just frames addressed to him.

CONFIG_IEEE802154_UPIPE_MAC4

This is the byte 4 of the MAC address.

CONFIG_IEEE802154_UPIPE_MAC5

This is the byte 5 of the MAC address.

CONFIG_IEEE802154_UPIPE_MAC6

This is the byte 6 of the MAC address.

CONFIG_IEEE802154_UPIPE_MAC7

This is the byte 7 of the MAC address.

CONFIG_IEEE802154_UPIPE_RANDOM_MAC

Generate a random MAC address dynamically.

CONFIG_IIS3DHHC

Enable driver for IIS3DHHC SPI-based accelerometer sensor.

CONFIG_IIS3DHHC_DRDY_INT1

Say Y to route data ready interrupt to INT1 pin. Say N to route to INT2 pin.

CONFIG_IIS3DHHC_NORM_MODE

Enable Sensor at 1KHz

CONFIG_IIS3DHHC_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_IIS3DHHC_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_IIS3DHHC_TRIGGER

CONFIG_IIS3DHHC_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_IIS3DHHC_TRIGGER_NONE

No trigger

CONFIG_IIS3DHHC_TRIGGER_OWN_THREAD

Use own thread

CONFIG_ILI9340

Enable driver for ILI9340 display driver.

CONFIG_ILI9340_LCD_ADAFRUIT_1480

Adafruit 2.2” TFT 1480

CONFIG_ILI9340_LCD_SEEED_TFTV2

Seeed 2.8” TFT v2.0

CONFIG_ILI9340_RGB565

RGB565

CONFIG_ILI9340_RGB888

RGB888

CONFIG_INTEL_GNA

Enable support for Intel’s GMM and Neural Network Accelerator

CONFIG_INTEL_GNA_INIT_PRIORITY

Device driver initialization priority.

CONFIG_INTEL_GNA_MAX_MODELS

Max. number of unique neural network models required in the system

CONFIG_INTEL_GNA_MAX_PENDING_REQUESTS

Maximum number of pending inference requests in the driver

CONFIG_INTEL_GNA_NAME

Name of the GNA device this device driver can use.

CONFIG_INTEL_GNA_POWER_MODE

Sets GNA operation mode for power saving Levels are: 0 ALWAYS_ON, GNA is always on with very minimal power save 1 CLOCK_GATED, GNA clock is gated when not active 2 POWER_GATED, GNA clock and power are gated when not active 3 ALWAYS_OFF, GNA is tuned off and never used in the system

CONFIG_IOAPIC

This option signifies that the target has an IO-APIC device. This capability allows IO-APIC-dependent code to be included.

CONFIG_IOAPIC_MASK_RTE

At boot, mask all IOAPIC RTEs if they may be in an undefined state. You don’t need this if the RTEs are either all guaranteed to be masked when the OS starts up, or a previous boot stage has done some IOAPIC configuration that needs to be preserved.

CONFIG_IOAPIC_NUM_RTES

This option indicates the maximum number of Redirection Table Entries (RTEs) (one per IRQ available to the IO-APIC) made available to the kernel, regardless of the number provided by the hardware itself. For most efficient usage of memory, it should match the number of IRQ lines needed by devices connected to the IO-APIC.

CONFIG_IPM

Include interrupt-based inter-processor mailboxes drivers in system configuration

CONFIG_IPM_CONSOLE_RECEIVER

Enable the receiving side of IPM console

CONFIG_IPM_CONSOLE_SENDER

Enable the sending side of IPM console

CONFIG_IPM_CONSOLE_STACK_SIZE

Each instance of the IPM console receiver driver creates a worker thread to print out incoming messages from the remote CPU. Specify the stack size for these threads here.

CONFIG_IPM_IMX

Driver for NXP i.MX messaging unit

CONFIG_IPM_IMX_MAX_DATA_SIZE

CONFIG_IPM_IMX_MAX_DATA_SIZE_16

There will be a single message type with id 0 and a maximum size of 16 bytes.

CONFIG_IPM_IMX_MAX_DATA_SIZE_4

There will be four message types with ids 0, 1, 2 or 3 and a maximum size of 4 bytes each.

CONFIG_IPM_IMX_MAX_DATA_SIZE_8

There will be two message types with ids 0 or 1 and a maximum size of 8 bytes each.

CONFIG_IPM_IMX_MAX_ID_VAL

CONFIG_IPM_MCUX

Driver for MCUX mailbox

CONFIG_IPM_MHU

Driver for SSE 200 MHU (Message Handling Unit)

CONFIG_IPM_MSG_CH_0_ENABLE

Enable IPM Message Channel 0

CONFIG_IPM_MSG_CH_0_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_0_TX

IPM Message TX Channel

CONFIG_IPM_MSG_CH_10_ENABLE

Enable IPM Message Channel 10

CONFIG_IPM_MSG_CH_10_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_10_TX

IPM Message TX Channel

CONFIG_IPM_MSG_CH_11_ENABLE

Enable IPM Message Channel 11

CONFIG_IPM_MSG_CH_11_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_11_TX

IPM Message TX Channel

CONFIG_IPM_MSG_CH_12_ENABLE

Enable IPM Message Channel 12

CONFIG_IPM_MSG_CH_12_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_12_TX

IPM Message TX Channel

CONFIG_IPM_MSG_CH_13_ENABLE

Enable IPM Message Channel 13

CONFIG_IPM_MSG_CH_13_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_13_TX

IPM Message TX Channel

CONFIG_IPM_MSG_CH_14_ENABLE

Enable IPM Message Channel 14

CONFIG_IPM_MSG_CH_14_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_14_TX

IPM Message TX Channel

CONFIG_IPM_MSG_CH_15_ENABLE

Enable IPM Message Channel 15

CONFIG_IPM_MSG_CH_15_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_15_TX

IPM Message TX Channel

CONFIG_IPM_MSG_CH_1_ENABLE

Enable IPM Message Channel 1

CONFIG_IPM_MSG_CH_1_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_1_TX

IPM Message TX Channel

CONFIG_IPM_MSG_CH_2_ENABLE

Enable IPM Message Channel 2

CONFIG_IPM_MSG_CH_2_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_2_TX

IPM Message TX Channel

CONFIG_IPM_MSG_CH_3_ENABLE

Enable IPM Message Channel 3

CONFIG_IPM_MSG_CH_3_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_3_TX

IPM Message TX Channel

CONFIG_IPM_MSG_CH_4_ENABLE

Enable IPM Message Channel 4

CONFIG_IPM_MSG_CH_4_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_4_TX

IPM Message TX Channel

CONFIG_IPM_MSG_CH_5_ENABLE

Enable IPM Message Channel 5

CONFIG_IPM_MSG_CH_5_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_5_TX

IPM Message TX Channel

CONFIG_IPM_MSG_CH_6_ENABLE

Enable IPM Message Channel 6

CONFIG_IPM_MSG_CH_6_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_6_TX

IPM Message TX Channel

CONFIG_IPM_MSG_CH_7_ENABLE

Enable IPM Message Channel 7

CONFIG_IPM_MSG_CH_7_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_7_TX

IPM Message TX Channel

CONFIG_IPM_MSG_CH_8_ENABLE

Enable IPM Message Channel 8

CONFIG_IPM_MSG_CH_8_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_8_TX

IPM Message TX Channel

CONFIG_IPM_MSG_CH_9_ENABLE

Enable IPM Message Channel 9

CONFIG_IPM_MSG_CH_9_RX

IPM Message RX Channel

CONFIG_IPM_MSG_CH_9_TX

IPM Message TX Channel

CONFIG_IPM_NRFX

Driver for Nordic nRF messaging unit, based on nRF IPC peripheral HW.

CONFIG_IPM_NRF_SINGLE_INSTANCE

Enable this option if the IPM device should have a single instance, instead of one per IPC message channel.

CONFIG_IPM_STM32_IPCC

Driver for stm32 IPCC mailboxes

CONFIG_IPM_STM32_IPCC_PROCID

use to define the Processor ID for IPCC access

CONFIG_ISL29035

Enable driver for the ISL29035 light sensor.

CONFIG_ISL29035_INTEGRATION_TIME_105K

105 ms

CONFIG_ISL29035_INTEGRATION_TIME_26

0.0256 ms

CONFIG_ISL29035_INTEGRATION_TIME_410

0.41 ms

CONFIG_ISL29035_INTEGRATION_TIME_6500

6.5 ms

CONFIG_ISL29035_INT_PERSIST_1

1

CONFIG_ISL29035_INT_PERSIST_16

16

CONFIG_ISL29035_INT_PERSIST_4

4

CONFIG_ISL29035_INT_PERSIST_8

8

CONFIG_ISL29035_LUX_RANGE_16K

16000

CONFIG_ISL29035_LUX_RANGE_1K

1000

CONFIG_ISL29035_LUX_RANGE_4K

4000

CONFIG_ISL29035_LUX_RANGE_64K

64000

CONFIG_ISL29035_MODE_ALS

Sensing mode for ambient light spectrum.

CONFIG_ISL29035_MODE_IR

Sensing mode for infrared spectrum.

CONFIG_ISL29035_THREAD_PRIORITY

Priority of thread used to handle the timer and threshold triggers.

CONFIG_ISL29035_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_ISL29035_TRIGGER

CONFIG_ISL29035_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_ISL29035_TRIGGER_NONE

No trigger

CONFIG_ISL29035_TRIGGER_OWN_THREAD

Use own thread

CONFIG_IWDG_STM32

Enable IWDG driver for STM32 line of MCUs

CONFIG_IWDG_STM32_START_AT_BOOT

Enable this setting to allow IWDG to be automatically started during device initialization. Note that once IWDG is started it must be reloaded before the counter reaches 0, otherwise the MCU will be reset.

CONFIG_IWDG_STM32_TIMEOUT

Set timeout value for IWDG in microseconds. The min timeout supported is 0.1ms, the max timeout is 26214.4ms.

CONFIG_KSCAN

Include Keyboard scan drivers in system config.

CONFIG_KSCAN_INIT_PRIORITY

Keyboard scan device driver initialization priority.

CONFIG_KSCAN_XEC

Enable the Microchip XEC Kscan IO driver.

CONFIG_KSCAN_XEC_COLUMN_SIZE

Adjust the value to your keyboard columns. The maximum column size for the Microchip XEC family is 18 (from 0 to 17).

CONFIG_KSCAN_XEC_DEBOUNCE_DOWN

Determines the time in msecs for debouncing a key press.

CONFIG_KSCAN_XEC_DEBOUNCE_UP

Determines the time in msecs for debouncing a key release.

CONFIG_KSCAN_XEC_POLL_PERIOD

Defines the poll period in msecs between between matrix scans.

CONFIG_KSCAN_XEC_ROW_SIZE

Adjust the value to your keyboard rows. The maximum column size for the Microchip XEC family is 8 (from 0 to 7).

CONFIG_KW41_DBG_TRACE

The value depends on your debugging needs. This generates an encoded trace of events without going to debug logging to avoid timing impact on running code. The buffer is post analyzed via the debugger.

CONFIG_LED

Include LED drivers in the system configuration.

CONFIG_LED_INIT_PRIORITY

System initialization priority for LED drivers.

CONFIG_LED_STRIP

Include LED strip drivers in the system configuration.

CONFIG_LED_STRIP_INIT_PRIORITY

System initialization priority for LED strip drivers.

CONFIG_LED_STRIP_RGB_SCRATCH

CONFIG_LEUART_GECKO

Enable the Gecko leuart driver.

CONFIG_LIS2DH

Enable SPI/I2C-based driver for LIS2DH, LIS3DH, LSM303DLHC, LIS2DH12, LSM303AGR triaxial accelerometer sensors.

CONFIG_LIS2DH_ACCEL_RANGE_16G

+/-16g

CONFIG_LIS2DH_ACCEL_RANGE_2G

+/-2g

CONFIG_LIS2DH_ACCEL_RANGE_4G

+/-4g

CONFIG_LIS2DH_ACCEL_RANGE_8G

+/-8g

CONFIG_LIS2DH_ACCEL_RANGE_RUNTIME

Set at runtime

CONFIG_LIS2DH_ODR_1

1Hz

CONFIG_LIS2DH_ODR_2

10Hz

CONFIG_LIS2DH_ODR_3

25Hz

CONFIG_LIS2DH_ODR_4

50Hz

CONFIG_LIS2DH_ODR_5

100Hz

CONFIG_LIS2DH_ODR_6

200Hz

CONFIG_LIS2DH_ODR_7

400Hz

CONFIG_LIS2DH_ODR_8

1.6KHz

CONFIG_LIS2DH_ODR_9_LOW

5KHz

CONFIG_LIS2DH_ODR_9_NORMAL

1.25KHz

CONFIG_LIS2DH_ODR_RUNTIME

Set at runtime

CONFIG_LIS2DH_OPER_MODE_HIGH_RES

high resolution (12 bit)

CONFIG_LIS2DH_OPER_MODE_LOW_POWER

low power (8 bit)

CONFIG_LIS2DH_OPER_MODE_NORMAL

normal (10 bit)

CONFIG_LIS2DH_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_LIS2DH_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_LIS2DH_TRIGGER

CONFIG_LIS2DH_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_LIS2DH_TRIGGER_NONE

No trigger

CONFIG_LIS2DH_TRIGGER_OWN_THREAD

Use own thread

CONFIG_LIS2DS12

Enable driver for LIS2DS12 accelerometer sensor driver

CONFIG_LIS2DS12_ENABLE_TEMP

Enable/disable temperature

CONFIG_LIS2DS12_FS

Specify the default accelerometer full-scale range. An X value for the config represents a range of +/- X G. Valid values are: 0: Full Scale selected at runtime 2: +/- 2g 4: +/- 4g 8: +/- 8g 16: +/- 16g

CONFIG_LIS2DS12_ODR

Specify the default accelerometer output data rate expressed in samples per second (Hz). 0: ODR selected at runtime 1: 12.5Hz 2: 25Hz 3: 50Hz 4: 100Hz 5: 200Hz 6: 400Hz 7: 800Hz

CONFIG_LIS2DS12_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_LIS2DS12_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_LIS2DS12_TRIGGER

CONFIG_LIS2DS12_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_LIS2DS12_TRIGGER_NONE

No trigger

CONFIG_LIS2DS12_TRIGGER_OWN_THREAD

Use own thread

CONFIG_LIS2DW12

Enable driver for LIS2DW12 accelerometer sensor driver

CONFIG_LIS2DW12_ACCEL_RANGE_16G

16G

CONFIG_LIS2DW12_ACCEL_RANGE_2G

2G

CONFIG_LIS2DW12_ACCEL_RANGE_4G

4G

CONFIG_LIS2DW12_ACCEL_RANGE_8G

8G

CONFIG_LIS2DW12_ACCEL_RANGE_RUNTIME

Set at runtime (Default 2G)

CONFIG_LIS2DW12_INT_PIN_1

int1

CONFIG_LIS2DW12_INT_PIN_2

int2

CONFIG_LIS2DW12_ODR_100

100 Hz

CONFIG_LIS2DW12_ODR_12_5

12.5 Hz

CONFIG_LIS2DW12_ODR_1600

1600 Hz

CONFIG_LIS2DW12_ODR_1_6

1.6 Hz

CONFIG_LIS2DW12_ODR_200

200 Hz

CONFIG_LIS2DW12_ODR_25

25 Hz

CONFIG_LIS2DW12_ODR_400

400 Hz

CONFIG_LIS2DW12_ODR_50

50 Hz

CONFIG_LIS2DW12_ODR_800

800 Hz

CONFIG_LIS2DW12_ODR_RUNTIME

Set at runtime (Default 100 Hz)

CONFIG_LIS2DW12_ONLY_SINGLE

single

CONFIG_LIS2DW12_POWER_MODE

Specify the sensor power mode 0: Low Power M1 1: Low Power M2 2: Low Power M3 3: Low Power M4 4: High Performance

CONFIG_LIS2DW12_PULSE

Enable pulse (single/double tap) detection

CONFIG_LIS2DW12_PULSE_LTNCY

When double-tap recognition is enabled, this register expresses the maximum time between two successive detected taps to determine a double-tap event. Where 0 equals 16*1/ODR and 1LSB = 32*1/ODR.

CONFIG_LIS2DW12_PULSE_QUIET

Expected quiet time after a tap detection: this register represents the time after the first detected tap in which there must not be any overthreshold event. Where 0 equals 2*1/ODR and 1LSB = 4*1/ODR.

CONFIG_LIS2DW12_PULSE_SHOCK

Maximum duration of over-threshold event: this register represents the maximum time of an over-threshold signal detection to be recognized as a tap event. Where 0 equals 4*1/ODR and 1LSB = 8*1/ODR.

CONFIG_LIS2DW12_PULSE_THSX

Threshold to start the pulse-event detection procedure on the X-axis. Threshold values for each axis are unsigned 5-bit corresponding to an 2g acceleration full-scale range.

CONFIG_LIS2DW12_PULSE_THSY

Threshold to start the pulse-event detection procedure on the Y-axis. Threshold values for each axis are unsigned 5-bit corresponding to an 2g acceleration full-scale range.

CONFIG_LIS2DW12_PULSE_THSZ

Threshold to start the pulse-event detection procedure on the Z-axis. Threshold values for each axis are unsigned 5-bit corresponding to an 2g acceleration full-scale range.

CONFIG_LIS2DW12_PULSE_X

Enable X axis for pulse

CONFIG_LIS2DW12_PULSE_Y

Enable Y axis for pulse

CONFIG_LIS2DW12_PULSE_Z

Enable Z axis for pulse

CONFIG_LIS2DW12_SINGLE_DOUBLE

single/double

CONFIG_LIS2DW12_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_LIS2DW12_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_LIS2DW12_TRIGGER

CONFIG_LIS2DW12_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_LIS2DW12_TRIGGER_NONE

No trigger

CONFIG_LIS2DW12_TRIGGER_OWN_THREAD

Use own thread

CONFIG_LIS2MDL

Enable driver for LIS2MDL I2C-based magnetometer sensor.

CONFIG_LIS2MDL_MAG_ODR_RUNTIME

Set magnetometer sampling frequency (ODR) at runtime (default: 10 Hz)

CONFIG_LIS2MDL_SPI_FULL_DUPLEX

Enable SPI 4wire mode (separated MISO and MOSI lines)

CONFIG_LIS2MDL_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_LIS2MDL_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_LIS2MDL_TRIGGER

CONFIG_LIS2MDL_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_LIS2MDL_TRIGGER_NONE

No trigger

CONFIG_LIS2MDL_TRIGGER_OWN_THREAD

Use own thread

CONFIG_LIS3MDL

Enable driver for LIS3MDL I2C-based magnetometer.

CONFIG_LIS3MDL_FS

Magnetometer full-scale range. An X value for the config represents a range of +/- X gauss. Valid values are 4, 8, 12 and 16.

CONFIG_LIS3MDL_ODR

Magnetometer output data rate expressed in samples per second. Data rates supported by the chip are 0.625, 1.25, 2.5, 5, 10, 20, 40, 80, 155, 300, 560 and 1000.

CONFIG_LIS3MDL_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_LIS3MDL_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_LIS3MDL_TRIGGER

CONFIG_LIS3MDL_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_LIS3MDL_TRIGGER_NONE

No trigger

CONFIG_LIS3MDL_TRIGGER_OWN_THREAD

Use own thread

CONFIG_LITEX_TIMER

This module implements a kernel device driver for LiteX Timer.

CONFIG_LOAPIC

This option selects local APIC as the interrupt controller.

CONFIG_LOAPIC_BASE_ADDRESS

This option specifies the base address of the Local APIC device.

CONFIG_LOAPIC_SPURIOUS_VECTOR

A special situation may occur when a processor raises its task priority to be greater than or equal to the level of the interrupt for which the processor INTR signal is currently being asserted. If at the time the INTA cycle is issued, the interrupt that was to be dispensed has become masked (programmed by software), the local APIC will deliver a spurious-interrupt vector. Dispensing the spurious-interrupt vector does not affect the ISR, so the handler for this vector should return without an EOI. From x86 manual Volume 3 Section 10.9.

CONFIG_LOAPIC_SPURIOUS_VECTOR_ID

IDT vector to use for spurious LOAPIC interrupts. Note that some arches (P6, Pentium) ignore the low 4 bits and fix them at 0xF. If this value is left at -1 the last entry in the IDT will be used.

CONFIG_LOAPIC_TIMER

This option selects LOAPIC timer as a system timer.

CONFIG_LOAPIC_TIMER_IRQ

This option specifies the IRQ used by the LOAPIC timer.

CONFIG_LOAPIC_TIMER_IRQ_PRIORITY

This options specifies the IRQ priority used by the LOAPIC timer.

CONFIG_LORA

Include LoRa drivers in the system configuration.

CONFIG_LORA_INIT_PRIORITY

System initialization priority for LoRa drivers.

CONFIG_LORA_SX1276

Enable LoRa driver for Semtech SX1276.

CONFIG_LP3943

Enable LED driver for LP3943.

LP3943 LED driver has 16 channels each with multi-programmable states at a specified rate. Each channel can drive up to 25 mA per LED.

CONFIG_LP5562

Enable LED driver for LP5562.

LP5562 LED driver has 4 channels (RGBW). Each channel can drive up to 25.5 mA per LED.

CONFIG_LPD880X_STRIP

Enable LED strip driver for daisy chains of LPD880x (LPD8803, LPD8806, or compatible) devices.

Each LPD880x LED driver chip has some output channels (3 channels for LPD8803, 6 for LPD8806), whose PWM duty cycle can be set at 7 bit resolution via a reduced SPI interface (MOSI and CLK lines only). Each chip also includes data and clock out pins for daisy chaining LED strips.

CONFIG_LPS22HB

Enable driver for LPS22HB I2C-based pressure and temperature sensor.

CONFIG_LPS22HB_SAMPLING_RATE

Sensor output data rate expressed in samples per second. Data rates supported by the chip are 1, 10, 25, 50, 75.

CONFIG_LPS22HH

Enable driver for LPS22HH I2C-based pressure and temperature sensor.

CONFIG_LPS22HH_SAMPLING_RATE

Sensor output data rate expressed in samples per second. Data rates supported by the chip are: 0: ODR selected at runtime 1: 1Hz 2: 10Hz 3: 25Hz 4: 50Hz 5: 75Hz 6: 100Hz 7: 200Hz

CONFIG_LPS22HH_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_LPS22HH_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_LPS22HH_TRIGGER

CONFIG_LPS22HH_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_LPS22HH_TRIGGER_NONE

No trigger

CONFIG_LPS22HH_TRIGGER_OWN_THREAD

Use own thread

CONFIG_LPS25HB

Enable driver for LPS25HB I2C-based pressure and temperature sensor.

CONFIG_LPS25HB_SAMPLING_RATE

Sensor output data rate expressed in samples per second. Data rates supported by the chip are 1, 7, 13, 25.

CONFIG_LPUART_1

Enable support for LPUART1 port in the driver. Say y here if you want to use LPUART1 device.

CONFIG_LSM303DLHC_MAGN

Enable driver for LSM303DLHC I2C-based triaxial magnetometer sensor.

CONFIG_LSM303DLHC_MAGN_ODR

0: 0.75Hz 1: 1.5 Hz 2: 3Hz 3: 7.5Hz 4: 15Hz 5: 30Hz 6: 75Hz 7: 220Hz

CONFIG_LSM303DLHC_MAGN_RANGE

1: +/-1.3 gauss 2: +/-1.9 gauss 3: +/-2.5 gauss 4: +/-4 gauss 5: +/-4.7 gauss 6: +/-5.6 gauss 7: +/-8.1 gauss

CONFIG_LSM6DS0

Enable driver for LSM6DS0 I2C-based accelerometer and gyroscope sensor.

CONFIG_LSM6DS0_ACCEL_ENABLE_X_AXIS

Enable/disable accelerometer X axis totally by stripping everything related in driver.

CONFIG_LSM6DS0_ACCEL_ENABLE_Y_AXIS

Enable/disable accelerometer Y axis totally by stripping everything related in driver.

CONFIG_LSM6DS0_ACCEL_ENABLE_Z_AXIS

Enable/disable accelerometer Z axis totally by stripping everything related in driver.

CONFIG_LSM6DS0_ACCEL_FULLSCALE

Specify the default accelerometer full-scale range. An X value for the config represents a range of +/- X G. Valid values are 2, 4, 8 and 16.

CONFIG_LSM6DS0_ACCEL_SAMPLING_RATE

Specify the default accelerometer output data rate expressed in samples per second (Hz). Data rates supported by the chip are 0, 10, 50, 119, 238, 476, 952.

CONFIG_LSM6DS0_ENABLE_TEMP

Enable/disable temperature totally by stripping everything related in driver.

CONFIG_LSM6DS0_GYRO_ENABLE_X_AXIS

Enable/disable gyroscope X axis totally by stripping everything related in driver.

CONFIG_LSM6DS0_GYRO_ENABLE_Y_AXIS

Enable/disable gyroscope Y axis totally by stripping everything related in driver.

CONFIG_LSM6DS0_GYRO_ENABLE_Z_AXIS

Enable/disable gyroscope Z axis totally by stripping everything related in driver.

CONFIG_LSM6DS0_GYRO_FULLSCALE

Specify the default gyroscope full-scale range. An X value for the config represents a range of +/- X degree per second. Valid values are 245, 500 and 2000.

CONFIG_LSM6DS0_GYRO_SAMPLING_RATE

Specify the default gyroscope output data rate expressed in samples per second (Hz). Data rates supported by the chip are 0, 15, 60, 119, 238, 476, 952.

CONFIG_LSM6DSL

Enable driver for LSM6DSL accelerometer and gyroscope sensor.

CONFIG_LSM6DSL_ACCEL_FS

Specify the default accelerometer full-scale range. An X value for the config represents a range of +/- X G. Valid values are: 0: Full Scale selected at runtime 2: +/- 2g 4: +/- 4g 8: +/- 8g 16: +/- 16g

CONFIG_LSM6DSL_ACCEL_ODR

Specify the default accelerometer output data rate expressed in samples per second (Hz). 0: ODR selected at runtime 1: 12.5Hz 2: 26Hz 3: 52Hz 4: 104Hz 5: 208Hz 6: 416Hz 7: 833Hz 8: 1660Hz 9: 3330Hz 10: 6660Hz

CONFIG_LSM6DSL_ENABLE_TEMP

Enable/disable temperature

CONFIG_LSM6DSL_EXT0_LIS2MDL

LIS2MDL

CONFIG_LSM6DSL_EXT0_LPS22HB

LPS22HB

CONFIG_LSM6DSL_GYRO_FS

Specify the default gyroscope full-scale range. An X value for the config represents a range of +/- X degree per second. Valid values are: 0: Full Scale selected at runtime 125: +/- 125dps 245: +/- 245dps 500: +/- 500dps 1000: +/- 1000dps 2000: +/- 2000dps

CONFIG_LSM6DSL_GYRO_ODR

Specify the default accelerometer output data rate expressed in samples per second (Hz). 0: ODR selected at runtime 1: 12.5Hz 2: 26Hz 3: 52Hz 4: 104Hz 5: 208Hz 6: 416Hz 7: 833Hz 8: 1660Hz 9: 3330Hz 10: 6660Hz

CONFIG_LSM6DSL_SENSORHUB

Enable/disable internal sensorhub

CONFIG_LSM6DSL_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_LSM6DSL_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_LSM6DSL_TRIGGER

CONFIG_LSM6DSL_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_LSM6DSL_TRIGGER_NONE

No trigger

CONFIG_LSM6DSL_TRIGGER_OWN_THREAD

Use own thread

CONFIG_LSM6DSO

Enable driver for LSM6DSO accelerometer and gyroscope sensor.

CONFIG_LSM6DSO_ACCEL_FS

Specify the default accelerometer full-scale range. An X value for the config represents a range of +/- X G. Valid values are: 0: Full Scale selected at runtime 2: +/- 2g 4: +/- 4g 8: +/- 8g 16: +/- 16g

CONFIG_LSM6DSO_ACCEL_ODR

Specify the default accelerometer output data rate expressed in samples per second (Hz). 0: ODR selected at runtime 1: 12.5Hz 2: 26Hz 3: 52Hz 4: 104Hz 5: 208Hz 6: 416Hz 7: 833Hz 8: 1660Hz 9: 3330Hz 10: 6660Hz

CONFIG_LSM6DSO_ENABLE_TEMP

Enable/disable temperature

CONFIG_LSM6DSO_EXT_HTS221

Enable HTS221 as external sensor

CONFIG_LSM6DSO_EXT_LIS2MDL

Enable LIS2MDL as external sensor

CONFIG_LSM6DSO_EXT_LPS22HB

Enable LPS22HB as external sensor

CONFIG_LSM6DSO_EXT_LPS22HH

Enable LPS22HH as external sensor

CONFIG_LSM6DSO_GYRO_FS

Specify the default gyroscope full-scale range. An X value for the config represents a range of +/- X degree per second. Valid values are: 0: Full Scale selected at runtime 125: +/- 125dps 250: +/- 250dps 500: +/- 500dps 1000: +/- 1000dps 2000: +/- 2000dps

CONFIG_LSM6DSO_GYRO_ODR

Specify the default accelerometer output data rate expressed in samples per second (Hz). 0: ODR selected at runtime 1: 12.5Hz 2: 26Hz 3: 52Hz 4: 104Hz 5: 208Hz 6: 416Hz 7: 833Hz 8: 1660Hz 9: 3330Hz 10: 6660Hz

CONFIG_LSM6DSO_INT_PIN_1

int1

CONFIG_LSM6DSO_INT_PIN_2

int2

CONFIG_LSM6DSO_SENSORHUB

Enable/disable internal sensorhub. You can enable a maximum of two external sensors (if more than two are enabled the system would enumerate only the first two found)

CONFIG_LSM6DSO_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_LSM6DSO_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_LSM6DSO_TRIGGER

CONFIG_LSM6DSO_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_LSM6DSO_TRIGGER_NONE

No trigger

CONFIG_LSM6DSO_TRIGGER_OWN_THREAD

Use own thread

CONFIG_LSM9DS0_GYRO

Enable driver for LSM9DS0 I2C-based gyroscope sensor.

CONFIG_LSM9DS0_GYRO_FULLSCALE_2000

2000 DPS

CONFIG_LSM9DS0_GYRO_FULLSCALE_245

245 DPS

CONFIG_LSM9DS0_GYRO_FULLSCALE_500

500 DPS

CONFIG_LSM9DS0_GYRO_FULLSCALE_RUNTIME

Enable alteration of full-scale attribute at runtime.

CONFIG_LSM9DS0_GYRO_SAMPLING_RATE_190

190 Hz

CONFIG_LSM9DS0_GYRO_SAMPLING_RATE_380

380 Hz

CONFIG_LSM9DS0_GYRO_SAMPLING_RATE_760

760 Hz

CONFIG_LSM9DS0_GYRO_SAMPLING_RATE_95

95 Hz

CONFIG_LSM9DS0_GYRO_SAMPLING_RATE_RUNTIME

Enable alteration of sampling rate frequency at runtime.

CONFIG_LSM9DS0_GYRO_THREAD_STACK_SIZE

Specify the internal thread stack size.

CONFIG_LSM9DS0_GYRO_TRIGGERS

Enable triggers

CONFIG_LSM9DS0_GYRO_TRIGGER_DRDY

Enable data ready trigger

CONFIG_LSM9DS0_MFD

Enable driver for LSM9DS0 I2C-based MFD sensor.

CONFIG_LSM9DS0_MFD_ACCEL_ENABLE

Enable/disable accelerometer totally by stripping everything related in driver.

CONFIG_LSM9DS0_MFD_ACCEL_ENABLE_X

Enable accelerometer X axis

CONFIG_LSM9DS0_MFD_ACCEL_ENABLE_Y

Enable accelerometer Y axis

CONFIG_LSM9DS0_MFD_ACCEL_ENABLE_Z

Enable accelerometer Z axis

CONFIG_LSM9DS0_MFD_ACCEL_FULL_SCALE_16

16G

CONFIG_LSM9DS0_MFD_ACCEL_FULL_SCALE_2

2G

CONFIG_LSM9DS0_MFD_ACCEL_FULL_SCALE_4

4G

CONFIG_LSM9DS0_MFD_ACCEL_FULL_SCALE_6

6G

CONFIG_LSM9DS0_MFD_ACCEL_FULL_SCALE_8

8G

CONFIG_LSM9DS0_MFD_ACCEL_FULL_SCALE_RUNTIME

Enable alteration of accelerometer full-scale attribute at runtime.

CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_0

0 Hz (power down)

CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_100

100 Hz

CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_12_5

12.5 Hz

CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_1600

1600 Hz

CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_200

200 Hz

CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_25

25 Hz

CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_3_125

3.125 Hz

CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_400

400 Hz

CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_50

50 Hz

CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_6_25

6.25 Hz

CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_800

800 Hz

CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_RUNTIME

Enable alteration of accelerometer sampling rate attribute at runtime.

CONFIG_LSM9DS0_MFD_MAGN_ENABLE

Enable/disable magnetometer totally by stripping everything related in driver.

CONFIG_LSM9DS0_MFD_MAGN_FULL_SCALE_12

12 Gauss

CONFIG_LSM9DS0_MFD_MAGN_FULL_SCALE_2

2 Gauss

CONFIG_LSM9DS0_MFD_MAGN_FULL_SCALE_4

4 Gauss

CONFIG_LSM9DS0_MFD_MAGN_FULL_SCALE_8

8 Gauss

CONFIG_LSM9DS0_MFD_MAGN_FULL_SCALE_RUNTIME

Enable alteration of magnetometer full-scale attribute at runtime.

CONFIG_LSM9DS0_MFD_MAGN_SAMPLING_RATE_100

100 Hz

CONFIG_LSM9DS0_MFD_MAGN_SAMPLING_RATE_12_5

12.5 Hz

CONFIG_LSM9DS0_MFD_MAGN_SAMPLING_RATE_25

25 Hz

CONFIG_LSM9DS0_MFD_MAGN_SAMPLING_RATE_3_125

3.125 Hz

CONFIG_LSM9DS0_MFD_MAGN_SAMPLING_RATE_50

50 Hz

CONFIG_LSM9DS0_MFD_MAGN_SAMPLING_RATE_6_25

6.25 Hz

CONFIG_LSM9DS0_MFD_MAGN_SAMPLING_RATE_RUNTIME

Enable alteration of magnetometer sampling rate attribute at runtime.

CONFIG_LSM9DS0_MFD_TEMP_ENABLE

Enable/disable temperature sensor totally by stripping everything related in driver.

CONFIG_MAX30101

MAX30101 Pulse Oximeter and Heart Rate Sensor

CONFIG_MAX30101_ADC_RGE

Set the ADC’s full-scale range. 0 = 7.81 pA/LSB 1 = 15.63 pA/LSB 2 = 31.25 pA/LSB 3 = 62.5 pA/LSB

CONFIG_MAX30101_FIFO_A_FULL

Set the trigger for the FIFO_A_FULL interrupt

CONFIG_MAX30101_FIFO_ROLLOVER_EN

Controls the behavior of the FIFO when the FIFO becomes completely filled with data. If set, the FIFO address rolls over to zero and the FIFO continues to fill with new data. If not set, then the FIFO is not updated until FIFO_DATA is read or the WRITE/READ pointer positions are changed.

CONFIG_MAX30101_HEART_RATE_MODE

Set to operate in heart rate only mode. The red LED channel is active.

CONFIG_MAX30101_LED1_PA

Set the pulse amplitude to control the LED1 (red) current. The actual measured LED current for each part can vary significantly due to the trimming methodology. 0x00 = 0.0 mA 0x01 = 0.2 mA 0x02 = 0.4 mA 0x0f = 3.1 mA 0xff = 50.0 mA

CONFIG_MAX30101_LED2_PA

Set the pulse amplitude to control the LED2 (IR) current. The actual measured LED current for each part can vary significantly due to the trimming methodology. 0x00 = 0.0 mA 0x01 = 0.2 mA 0x02 = 0.4 mA 0x0f = 3.1 mA 0xff = 50.0 mA

CONFIG_MAX30101_LED3_PA

Set the pulse amplitude to control the LED3 (green) current. The actual measured LED current for each part can vary significantly due to the trimming methodology. 0x00 = 0.0 mA 0x01 = 0.2 mA 0x02 = 0.4 mA 0x0f = 3.1 mA 0xff = 50.0 mA

CONFIG_MAX30101_MULTI_LED_MODE

Set to operate in multi-LED mode. The green, red, and/or IR LED channels are active.

CONFIG_MAX30101_SLOT1

Set which LED and pulse amplitude are active in time slot 1. 0: None (disabled) 1: LED1 (red), LED1_PA 2: LED2 (IR), LED2_PA 3: LED3 (green), LED3_PA 4: None (disabled) 5: LED1 (red), PILOT_PA 6: LED2 (IR), PILOT_PA 7: LED3 (green), PILOT_PA

CONFIG_MAX30101_SLOT2

Set which LED and pulse amplitude are active in time slot 2. 0: None (disabled) 1: LED1 (red), LED1_PA 2: LED2 (IR), LED2_PA 3: LED3 (green), LED3_PA 4: None (disabled) 5: LED1 (red), PILOT_PA 6: LED2 (IR), PILOT_PA 7: LED3 (green), PILOT_PA

CONFIG_MAX30101_SLOT3

Set which LED and pulse amplitude are active in time slot 3. 0: None (disabled) 1: LED1 (red), LED1_PA 2: LED2 (IR), LED2_PA 3: LED3 (green), LED3_PA 4: None (disabled) 5: LED1 (red), PILOT_PA 6: LED2 (IR), PILOT_PA 7: LED3 (green), PILOT_PA

CONFIG_MAX30101_SLOT4

Set which LED and pulse amplitude are active in time slot 4. 0: None (disabled) 1: LED1 (red), LED1_PA 2: LED2 (IR), LED2_PA 3: LED3 (green), LED3_PA 4: None (disabled) 5: LED1 (red), PILOT_PA 6: LED2 (IR), PILOT_PA 7: LED3 (green), PILOT_PA

CONFIG_MAX30101_SMP_AVE

To reduce the amount of data throughput, adjacent samples (in each individual channel) can be averaged and decimated on the chip by setting this register. Set to 0 for no averaging. 0 = 1 sample (no averaging) 1 = 2 samples 2 = 4 samples 3 = 8 samples 4 = 16 samples 5 = 32 samples 6 = 32 samples 7 = 32 samples

CONFIG_MAX30101_SPO2_MODE

Set to operate in SpO2 mode. The red and IR LED channels are active.

CONFIG_MAX30101_SR

Set the effective sampling rate with one sample consisting of one pulse/conversion per active LED channel. In SpO2 mode, these means one IR pulse/conversion and one red pulse/conversion per sample period. 0 = 50 Hz 1 = 100 Hz 2 = 200 Hz 3 = 400 Hz 4 = 800 Hz 5 = 1000 Hz 6 = 1600 Hz 7 = 3200 Hz

CONFIG_MAX44009

Enable driver for MAX44009 light sensors.

CONFIG_MAX_IRQ_PER_AGGREGATOR

The maximum number of interrupt inputs to any aggregator in the system.

CONFIG_MCHP_XEC_RTOS_TIMER

This module implements a kernel device driver for the Microchip XEC series RTOS timer and provides the standard “system clock driver” interfaces.

CONFIG_MCP9808

Enable driver for MCP9808 temperature sensor.

CONFIG_MCP9808_THREAD_PRIORITY

MCP9808 thread priority

CONFIG_MCP9808_THREAD_STACK_SIZE

Sensor delayed work thread stack size

CONFIG_MCP9808_TRIGGER

CONFIG_MCP9808_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_MCP9808_TRIGGER_NONE

No trigger

CONFIG_MCP9808_TRIGGER_OWN_THREAD

Use own thread

CONFIG_MCR20A_CLK_OUT_16MHZ

16 MHz

CONFIG_MCR20A_CLK_OUT_1MHZ

1 MHz

CONFIG_MCR20A_CLK_OUT_250KHZ

250 kHz

CONFIG_MCR20A_CLK_OUT_32768HZ

32768 Hz

CONFIG_MCR20A_CLK_OUT_32MHZ

32 MHz

CONFIG_MCR20A_CLK_OUT_4MHZ

4 MHz

CONFIG_MCR20A_CLK_OUT_62500HZ

62500 Hz

CONFIG_MCR20A_CLK_OUT_8MHZ

8 MHz

CONFIG_MCR20A_CLK_OUT_DISABLED

Disabled

CONFIG_MCR20A_IS_PART_OF_KW2XD_SIP

If this option is set, the driver does not perform a hardware reset and the CLK_OUT frequency is not set, instead these settings are performed during the initialization of the SoC.

CONFIG_MCUX_ELCDIF_PANEL_RK043FN02H

Rocktech rk043fn02h-ct

CONFIG_MCUX_ELCDIF_POOL_BLOCK_ALIGN

Byte alignment in the frame buffer memory pool.

CONFIG_MCUX_ELCDIF_POOL_BLOCK_MAX

Maximum block size in the frame buffer memory pool.

CONFIG_MCUX_ELCDIF_POOL_BLOCK_MIN

Minimum block size in the frame buffer memory pool.

CONFIG_MCUX_ELCDIF_POOL_BLOCK_NUM

Number of blocks in the frame buffer memory pool.

CONFIG_MICROBIT_DISPLAY

Enable this to be able to display images and text on the 5x5 LED matrix display on the BBC micro:bit.

CONFIG_MICROBIT_DISPLAY_STR_MAX

This value specifies the maximum length of strings that can be displayed using the mb_display_string() and mb_display_print() APIs.

CONFIG_MODEM

Enable config options for modem drivers.

CONFIG_MODEM_CMD_HANDLER

This generic command handler uses a modem interface to process incoming data and hand it back to the modem driver via callbacks defined for: - modem responses - unsolicited messages - specified handlers for current operation To configure this layer for use, create a modem_cmd_handler_data object and pass it’s reference to modem_cmd_handler_init() along with the modem_cmd_handler reference from your modem_context object.

CONFIG_MODEM_CMD_HANDLER_MAX_PARAM_COUNT

This option sets the maximum number of parameters which may be parsed by the command handler. This is also limited by the length of the match_buf (match_buf_len) field as it needs to be large enough to hold a single line of data (ending with /r).

CONFIG_MODEM_CONTEXT

This driver allows modem drivers to communicate with an interface using custom defined protocols. Driver doesn’t inspect received data and all aspects of received protocol data are handled by application work method provided. This driver combines abstractions for: modem interface, command handler, pin config and socket handling each of which will need to be configured.

CONFIG_MODEM_CONTEXT_MAX_NUM

Maximum number of modem contexts to handle. For most purposes this should stay at 1.

CONFIG_MODEM_CONTEXT_VERBOSE_DEBUG

Enabling this setting will turn on VERY heavy debugging from the modem context helper. Do NOT leave on for production.

CONFIG_MODEM_GSM_APN

Specify Access Point Name, i.e. the name to identify Internet IP GPRS cellular data context.

CONFIG_MODEM_GSM_INIT_PRIORITY

The GSM modem is initialized in POST_KERNEL using priority in the range 0-99.

CONFIG_MODEM_GSM_PPP

Enable GSM modems that support standard AT commands and PPP.

CONFIG_MODEM_GSM_UART_NAME

UART device name the modem is connected to

CONFIG_MODEM_IFACE_UART

To configure this layer for use, create a modem_iface_uart_data object and pass it’s reference to modem_iface_uart_init() along with the modem_iface reference from your modem_context object and the UART device name.

CONFIG_MODEM_RECEIVER

This driver allows modem drivers to communicate over UART with custom defined protocols. Driver doesn’t inspect received data and all aspects of received protocol data are handled by application via work method provided. This driver differs from the pipe UART driver in that callbacks are executed in a different work queue and data is passed around in k_pipe structures.

CONFIG_MODEM_RECEIVER_MAX_CONTEXTS

Maximum number of modem receiver contexts to handle. For most purposes this should stay at 1.

CONFIG_MODEM_SHELL

Activate shell module that provides modem utilities like sending a command to the modem UART.

CONFIG_MODEM_SOCKET

This layer provides much of the groundwork for keeping track of modem “sockets” throughout their lifecycle (from the initial offload API calls through the command handler call back layers). To configure this layer for use, create a modem_socket_config object with your socket data and pass it’s reference to modem_socket_init().

CONFIG_MODEM_SOCKET_PACKET_COUNT

As the modem indicates more data is available to be received, these values are organized into “packets”. This setting limits the maximum number of packet sizes the socket can keep track of.

CONFIG_MODEM_UBLOX_SARA

Choose this setting to enable u-blox SARA-R4 LTE-CatM1/NB-IoT modem driver.

CONFIG_MODEM_UBLOX_SARA_R4

Enable support for SARA-R4 modem

CONFIG_MODEM_UBLOX_SARA_R4_APN

This setting is used in the AT+CGDCONT command to set the APN name for the network connection context. This value is specific to the network provider and may need to be changed.

CONFIG_MODEM_UBLOX_SARA_R4_INIT_PRIORITY

u-blox SARA-R4 device driver initialization priority. Do not mess with it unless you know what you are doing. Note that the priority needs to be lower than the net stack so that it can start before the networking sub-system.

CONFIG_MODEM_UBLOX_SARA_R4_MANUAL_MCCMNO

This setting is used in the AT+COPS command to set the MCC/MNO for the network connection context. This value is specific to the network provider and may need to be changed if auto is not selected.

CONFIG_MODEM_UBLOX_SARA_R4_NAME

Driver name

CONFIG_MODEM_UBLOX_SARA_R4_RX_STACK_SIZE

This stack is used by the u-blox SARA-R4 RX thread.

CONFIG_MODEM_UBLOX_SARA_R4_RX_WORKQ_STACK_SIZE

This stack is used by the work queue to pass off net_pkt data to the rest of the network stack, letting the rx thread continue processing data.

CONFIG_MODEM_UBLOX_SARA_U2

Enable support for SARA-U2 modem

CONFIG_MODEM_WNCM14A2A

Choose this setting to enable Wistron WNC-M14A2A LTE-M modem driver. NOTE: Currently the pin settings only work with FRDM K64F shield.

CONFIG_MODEM_WNCM14A2A_APN_NAME

This setting is used in the AT%PDNSET command to set the APN name for the network connection context. Normally, don’t need to change this value.

CONFIG_MODEM_WNCM14A2A_INIT_PRIORITY

WNC-M14A2A device driver initialization priority. Do not mess with it unless you know what you are doing. Note that the priority needs to be lower than the net stack so that it can start before the networking sub-system.

CONFIG_MODEM_WNCM14A2A_RX_STACK_SIZE

This stack is used by the WNCM14A2A RX thread.

CONFIG_MODEM_WNCM14A2A_RX_WORKQ_STACK_SIZE

This stack is used by the work queue to pass off net_pkt data to the rest of the network stack, letting the rx thread continue processing data.

CONFIG_MPU6050

Enable driver for MPU6050 I2C-based six-axis motion tracking device.

CONFIG_MPU6050_ACCEL_FS

Magnetometer full-scale range. An X value for the config represents a range of +/- X g. Valid values are 2, 4, 8 and 16.

CONFIG_MPU6050_GYRO_FS

Gyroscope full-scale range. An X value for the config represents a range of +/- X degrees/second. Valid values are 250, 500, 1000, 2000.

CONFIG_MPU6050_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_MPU6050_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_MPU6050_TRIGGER

CONFIG_MPU6050_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_MPU6050_TRIGGER_NONE

No trigger

CONFIG_MPU6050_TRIGGER_OWN_THREAD

Use own thread

CONFIG_MPU9150

Enable this config option if the AK8975 sensor is part of a MPU9150 chip.

CONFIG_MPU9150_I2C_ADDR

I2C address of the MPU9150. If the driver for MPU6050 is enabled, its address will be used and this option made unavailable.

CONFIG_MS5607

Enable driver for MS5607 pressure and temperature sensor.

CONFIG_MS5607_PRES_OVER_1024X

x1024

CONFIG_MS5607_PRES_OVER_2048X

x2048

CONFIG_MS5607_PRES_OVER_256X

x256

CONFIG_MS5607_PRES_OVER_4096X

x4096

CONFIG_MS5607_PRES_OVER_512X

x512

CONFIG_MS5607_TEMP_OVER_1024X

x1024

CONFIG_MS5607_TEMP_OVER_2048X

x2048

CONFIG_MS5607_TEMP_OVER_256X

x256

CONFIG_MS5607_TEMP_OVER_4096X

x4096

CONFIG_MS5607_TEMP_OVER_512X

x512

CONFIG_MS5837

Enable driver for MS5837 pressure and temperature sensor.

CONFIG_MULTI_LEVEL_INTERRUPTS

Multiple levels of interrupts are normally used to increase the number of addressable interrupts in a system. For example, if two levels are used, a second level interrupt aggregator would combine all interrupts routed to it into one IRQ line in the first level interrupt controller. If three levels are used, a third level aggregator combines its input interrupts into one IRQ line at the second level. The number of interrupt levels is usually determined by the hardware. (The term “aggregator” here means “interrupt controller”.)

CONFIG_NATIVE_POSIX_CONSOLE

Use the host terminal (where the native_posix binary was launched) for the Zephyr console

CONFIG_NATIVE_POSIX_CONSOLE_INIT_PRIORITY

Device driver initialization priority.

CONFIG_NATIVE_POSIX_STDIN_CONSOLE

No current use. Kept only as there is plans to start using these drivers with the shell

CONFIG_NATIVE_POSIX_STDOUT_CONSOLE

Zephyr’s printk messages will be directed to the host terminal stdout.

CONFIG_NATIVE_POSIX_TIMER

This module implements a kernel device driver for the native_posix HW timer model

CONFIG_NATIVE_STDIN_POLL_PERIOD

In ms, polling period for stdin

CONFIG_NATIVE_UART_0_ON_OWN_PTY

Connect this UART to its own pseudoterminal. This is the preferred option for users who want to use Zephyr’s shell. Moreover this option does not conflict with any other native_posix backend which may use the calling shell standard input/output.

CONFIG_NATIVE_UART_0_ON_STDINOUT

Connect this UART to the stdin & stdout of the calling shell/terminal which invoked the native_posix executable. This is good enough for automated testing, or when feeding from a file/pipe. Note that other, non UART messages, will also be printed to the terminal. This option should NOT be used in conjunction with NATIVE_POSIX_STDIN_CONSOLE It is strongly discouraged to try to use this option with the new shell interactively, as the default terminal configuration is NOT appropriate for interactive use.

CONFIG_NATIVE_UART_AUTOATTACH_DEFAULT_CMD

If the native_posix executable is called with the –attach_uart command line option, this will be the default command which will be run to attach a new terminal to the 1st UART. Note that this command must have one, and only one, ‘%s’ as placeholder for the pseudoterminal device name (e.g. /dev/pts/35) This is only applicable if the UART_0 is configured to use its own PTY with NATIVE_UART_0_ON_OWN_PTY. The 2nd UART will not be affected by this option.

CONFIG_NET_LOOPBACK

Net loopback driver

CONFIG_NET_PPP

Point-to-point (PPP) UART based driver

CONFIG_NET_PPP_DRV_NAME

This option sets the driver name

CONFIG_NET_PPP_UART_PIPE_BUF_LEN

This options sets the size of the UART pipe buffer where data is being read to.

CONFIG_NET_PPP_VERIFY_FCS

If you have a reliable link, then it might make sense to disable this as it takes some time to verify the received packet.

CONFIG_NEURAL_NET_ACCEL

Enable support for Neural Network Accelerators

CONFIG_NORDIC_QSPI_NOR

Enable support for nrfx QSPI driver with EasyDMA.

CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE

When CONFIG_FLASH_PAGE_LAYOUT is used this driver will support that API. By default the page size corresponds to the block size (65536). Other option include the sector size (4096).

CONFIG_NORDIC_QSPI_NOR_INIT_PRIORITY

Device driver initialization priority.

CONFIG_NORDIC_QSPI_NOR_QE_BIT

Quad Enable bit number in Status Register

CONFIG_NRFX_DPPI

Enable DPPI allocator

CONFIG_NRFX_PPI

Enable PPI allocator

CONFIG_NRFX_TIMER

Enable TIMER driver

CONFIG_NRFX_TIMER0

Enable TIMER0 instance

CONFIG_NRFX_TIMER1

Enable TIMER1 instance

CONFIG_NRFX_TIMER2

Enable TIMER2 instance

CONFIG_NRFX_TIMER3

Enable TIMER3 instance

CONFIG_NRFX_TIMER4

Enable TIMER4 instance

CONFIG_NRFX_WDT0

Enable support for nrfx WDT instance 0.

CONFIG_NRFX_WDT1

Enable support for nrfx WDT instance 1.

CONFIG_NRF_RTC_TIMER

This module implements a kernel device driver for the nRF Real Time Counter NRF_RTC1 and provides the standard “system clock driver” interfaces.

CONFIG_NRF_UARTE_PERIPHERAL

CONFIG_NRF_UART_PERIPHERAL

CONFIG_NUM_2ND_LEVEL_AGGREGATORS

The number of level 2 interrupt aggregators to support. Each aggregator can manage at most MAX_IRQ_PER_AGGREGATOR level 2 interrupts.

CONFIG_NUM_3RD_LEVEL_AGGREGATORS

The number of level 3 interrupt aggregators to support. Each aggregator can manage at most MAX_IRQ_PER_AGGREGATOR level 3 interrupts.

CONFIG_OPT3001

Enable driver for OPT3001 light sensors.

CONFIG_PA_BOOST_PIN

Antenna connected to PA_BOOST pin.

CONFIG_PA_RFO_PIN

Antenna connected to PA_RFO pin.

CONFIG_PCA9633

Enable LED driver for PCA9633.

PCA9633 LED driver has 4 channels each with multi-programmable states. Each channel can drive up to 25 mA per LED.

CONFIG_PCIE

This option enables support for new PCI(e) drivers.

CONFIG_PCIE_MSI

Use Message-Signaled Interrupts where possible. With this option enabled, PCI(e) devices which support MSI will be configured (at runtime) to use them. This is typically required for PCIe devices to generate interrupts at all.

CONFIG_PCIE_SHELL

Enable commands for debugging PCI(e) using the built-in shell.

CONFIG_PINMUX

Enable board pinmux driver

CONFIG_PINMUX_BEETLE

Enable driver for ARM V2M Beetle Pin multiplexer.

CONFIG_PINMUX_CC13XX_CC26XX

Enable the TI SimpleLink CC13xx / CC26xx pinmux driver.

CONFIG_PINMUX_ESP32

Enable driver for ESP32 Pin multiplexer.

CONFIG_PINMUX_HSDK

Enable driver for ARC HSDK I/O pin mux.

CONFIG_PINMUX_INIT_PRIORITY

Pinmux driver initialization priority. Pinmux driver almost certainly should be initialized before the rest of hardware devices (which may need specific pins already configured for them), and usually after generic GPIO drivers. Thus, its priority should be between KERNEL_INIT_PRIORITY_DEFAULT and KERNEL_INIT_PRIORITY_DEVICE. There are exceptions to this rule for particular boards. Don’t change this value unless you know what you are doing.

CONFIG_PINMUX_INTEL_S1000

Enable driver for Intel S1000 I/O multiplexer.

CONFIG_PINMUX_MCUX

Enable the MCUX pinmux driver.

CONFIG_PINMUX_MCUX_LPC

Enable the MCUX LPC pinmux driver.

CONFIG_PINMUX_MCUX_LPC_PORT0

Enable Port 0.

CONFIG_PINMUX_MCUX_LPC_PORT0_NAME

Pinmux Port 0 driver name

CONFIG_PINMUX_MCUX_LPC_PORT1

Enable Port 1.

CONFIG_PINMUX_MCUX_LPC_PORT1_NAME

Pinmux Port 1 driver name

CONFIG_PINMUX_MCUX_PORTA

Enable Port A.

CONFIG_PINMUX_MCUX_PORTA_NAME

Pinmux Port A driver name

CONFIG_PINMUX_MCUX_PORTB

Enable Port B.

CONFIG_PINMUX_MCUX_PORTB_NAME

Pinmux Port B driver name

CONFIG_PINMUX_MCUX_PORTC

Enable Port C.

CONFIG_PINMUX_MCUX_PORTC_NAME

Pinmux Port C driver name

CONFIG_PINMUX_MCUX_PORTD

Enable Port D.

CONFIG_PINMUX_MCUX_PORTD_NAME

Pinmux Port D driver name

CONFIG_PINMUX_MCUX_PORTE

Enable Port E.

CONFIG_PINMUX_MCUX_PORTE_NAME

Pinmux Port E driver name

CONFIG_PINMUX_NAME

The name of the pinmux driver.

CONFIG_PINMUX_RV32M1

Enable the RV32M1 pinmux driver.

CONFIG_PINMUX_RV32M1_PORTA

Enable Port A.

CONFIG_PINMUX_RV32M1_PORTA_NAME

Pinmux Port A driver name

CONFIG_PINMUX_RV32M1_PORTB

Enable Port B.

CONFIG_PINMUX_RV32M1_PORTB_NAME

Pinmux Port B driver name

CONFIG_PINMUX_RV32M1_PORTC

Enable Port C.

CONFIG_PINMUX_RV32M1_PORTC_NAME

Pinmux Port C driver name

CONFIG_PINMUX_RV32M1_PORTD

Enable Port D.

CONFIG_PINMUX_RV32M1_PORTD_NAME

Pinmux Port D driver name

CONFIG_PINMUX_RV32M1_PORTE

Enable Port E.

CONFIG_PINMUX_RV32M1_PORTE_NAME

Pinmux Port E driver name

CONFIG_PINMUX_SAM0

Enable support for the Atmel SAM0 PORT pin multiplexer.

CONFIG_PINMUX_SIFIVE

Enable driver for the SiFive Freedom SOC pinmux driver

CONFIG_PINMUX_SIFIVE_0_NAME

SIFIVE pinmux 0 driver name

CONFIG_PINMUX_STM32

Enable pin multiplexer for STM32 MCUs

CONFIG_PINMUX_STM32_DEVICE_INITIALIZATION_PRIORITY

This option controls the priority of pinmux device initialization. Higher priority ensures that the device is initialized earlier in the startup cycle. Note that the pinmux device needs to be initialized after clock control device, but possibly before all other devices. If unsure, leave at default value 2

CONFIG_PINMUX_XEC

Enable the Microchip XEC pinmux driver.

CONFIG_PINMUX_XEC_GPIO000_036

Enable Port 000-036 or what would be equivalent to Port A.

CONFIG_PINMUX_XEC_GPIO000_036_NAME

Pinmux Port 000_036 driver name

CONFIG_PINMUX_XEC_GPIO040_076

Enable Port 040-076 or what would be equivalent to Port B

CONFIG_PINMUX_XEC_GPIO040_076_NAME

Pinmux Port 040_076 driver name

CONFIG_PINMUX_XEC_GPIO100_136

Enable Port 100-136 or what would be equivalent to Port C

CONFIG_PINMUX_XEC_GPIO100_136_NAME

Pinmux Port 100_136 driver name

CONFIG_PINMUX_XEC_GPIO140_176

Enable Port 140-176 or what would be equivalent to Port C

CONFIG_PINMUX_XEC_GPIO140_176_NAME

Pinmux Port 140_176 driver name

CONFIG_PINMUX_XEC_GPIO200_236

Enable Port 200-236 or what would be equivalent to Port D

CONFIG_PINMUX_XEC_GPIO200_236_NAME

Pinmux Port 200_236 driver name

CONFIG_PINMUX_XEC_GPIO240_276

Enable Port 240-276 or what would be equivalent to Port E

CONFIG_PINMUX_XEC_GPIO240_276_NAME

Pinmux Port 200_276 driver name

CONFIG_PLIC

Platform Level Interrupt Controller provides support for external interrupt lines defined by the RISC-V SoC;

CONFIG_PMS7003

Enable driver for pms7003 particulate matter sensor.

CONFIG_PMS7003_DRIVER_NAME

Driver name

CONFIG_PMS7003_UART_DEVICE

UART device

CONFIG_PPP_CLIENT_CLIENTSERVER

This is only necessary if a ppp connection should be established with a Microsoft Windows PC.

CONFIG_PPP_MAC_ADDR

Specify a MAC address for the PPP interface in the form of six hex 8-bit chars separated by colons (e.g.: aa:33:cc:22:e2:c0). The default is an empty string, which means the code will make 00:00:5E:00:53:XX, where XX will be random.

CONFIG_PS2

Include PS/2 drivers in system config.

CONFIG_PS2_INIT_PRIORITY

PS/2 device driver initialization priority. There isn’t any critical component relying on this priority at the moment.

CONFIG_PS2_XEC

Enable the Microchip XEC PS2 IO driver. The driver also depends on the KBC 8042 keyboard controller.

CONFIG_PS2_XEC_0

Enable PS2 0.

CONFIG_PS2_XEC_1

Enable PS2 1.

CONFIG_PTP_CLOCK

Enable options for Precision Time Protocol Clock drivers.

CONFIG_PTP_CLOCK_MCUX

Enable MCUX PTP clock support.

CONFIG_PTP_CLOCK_SAM_GMAC

Enable SAM GMAC PTP Clock support.

CONFIG_PWM

Enable config options for PWM drivers.

CONFIG_PWM_0

Enable PWM port 0

CONFIG_PWM_1

Enable PWM port 1

CONFIG_PWM_2

Enable PWM port 2

CONFIG_PWM_3

Enable PWM port 3

CONFIG_PWM_4

Enable PWM port 4

CONFIG_PWM_DW

Enable driver to utilize PWM on the DesignWare Timer IP block. Care must be taken if one is also to use the timer feature, as they both use the same set of registers.

CONFIG_PWM_DW_0_DRV_NAME

Specify the device name for the DesignWare PWM driver.

CONFIG_PWM_IMX

Enable support for i.MX pwm driver.

CONFIG_PWM_LED_ESP32

This option enables the PWM LED driver for ESP32 family of processors. Say y if you wish to use PWM LED port on ESP32.

CONFIG_PWM_LED_ESP32_DEV_NAME_0

Specify the device name for the PWM driver.

CONFIG_PWM_LED_ESP32_HS_CH

Set high speed channels

CONFIG_PWM_LED_ESP32_HS_CH0

Enable channel 0

CONFIG_PWM_LED_ESP32_HS_CH0_GPIO

GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39.

CONFIG_PWM_LED_ESP32_HS_CH0_TIMER

Timer source channel, allowed values: 0 - 4.

CONFIG_PWM_LED_ESP32_HS_CH1

Enable channel 1

CONFIG_PWM_LED_ESP32_HS_CH1_GPIO

GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39.

CONFIG_PWM_LED_ESP32_HS_CH1_TIMER

Timer source channel, allowed values: 0 - 4.

CONFIG_PWM_LED_ESP32_HS_CH2

Enable channel 2

CONFIG_PWM_LED_ESP32_HS_CH2_GPIO

GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39.

CONFIG_PWM_LED_ESP32_HS_CH2_TIMER

Timer source channel, allowed values: 0 - 4.

CONFIG_PWM_LED_ESP32_HS_CH3

Enable channel 3

CONFIG_PWM_LED_ESP32_HS_CH3_GPIO

GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39.

CONFIG_PWM_LED_ESP32_HS_CH3_TIMER

Timer source channel, allowed values: 0 - 4.

CONFIG_PWM_LED_ESP32_HS_CH4

Enable channel 4

CONFIG_PWM_LED_ESP32_HS_CH4_GPIO

GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39.

CONFIG_PWM_LED_ESP32_HS_CH4_TIMER

Timer source channel, allowed values: 0 - 4.

CONFIG_PWM_LED_ESP32_HS_CH5

Enable channel 5

CONFIG_PWM_LED_ESP32_HS_CH5_GPIO

GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39.

CONFIG_PWM_LED_ESP32_HS_CH5_TIMER

Timer source channel, allowed values: 0 - 4.

CONFIG_PWM_LED_ESP32_HS_CH6

Enable channel 6

CONFIG_PWM_LED_ESP32_HS_CH6_GPIO

GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39.

CONFIG_PWM_LED_ESP32_HS_CH6_TIMER

Timer source channel, allowed values: 0 - 4.

CONFIG_PWM_LED_ESP32_HS_CH7

Enable channel 7

CONFIG_PWM_LED_ESP32_HS_CH7_GPIO

GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39.

CONFIG_PWM_LED_ESP32_HS_CH7_TIMER

Timer source channel, allowed values: 0 - 4.

CONFIG_PWM_LED_ESP32_HS_TIMER

Set high speed timers

CONFIG_PWM_LED_ESP32_HS_TIMER0

Set timer 0

CONFIG_PWM_LED_ESP32_HS_TIMER0_BIT_NUM

PWM timer precision, allowed values: 10 - 15.

CONFIG_PWM_LED_ESP32_HS_TIMER0_FREQ

Set frequency

CONFIG_PWM_LED_ESP32_HS_TIMER1

Set timer 1

CONFIG_PWM_LED_ESP32_HS_TIMER1_BIT_NUM

PWM timer precision, allowed values: 10 - 15.

CONFIG_PWM_LED_ESP32_HS_TIMER1_FREQ

Set frequency

CONFIG_PWM_LED_ESP32_HS_TIMER2

Set timer 2

CONFIG_PWM_LED_ESP32_HS_TIMER2_BIT_NUM

PWM timer precision, allowed values: 10 - 15.

CONFIG_PWM_LED_ESP32_HS_TIMER2_FREQ

Set frequency

CONFIG_PWM_LED_ESP32_HS_TIMER3

Set timer 3

CONFIG_PWM_LED_ESP32_HS_TIMER3_BIT_NUM

PWM timer precision, allowed values: 10 - 15.

CONFIG_PWM_LED_ESP32_HS_TIMER3_FREQ

Set frequency

CONFIG_PWM_LED_ESP32_LS_CH

Set low speed channels

CONFIG_PWM_LED_ESP32_LS_CH0

Enable channel 0

CONFIG_PWM_LED_ESP32_LS_CH0_GPIO

GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39.

CONFIG_PWM_LED_ESP32_LS_CH0_TIMER

Timer source channel, allowed values: 0 - 4.

CONFIG_PWM_LED_ESP32_LS_CH1

Enable channel 1

CONFIG_PWM_LED_ESP32_LS_CH1_GPIO

GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39.

CONFIG_PWM_LED_ESP32_LS_CH1_TIMER

Timer source channel, allowed values: 0 - 4.

CONFIG_PWM_LED_ESP32_LS_CH2

Enable channel 2

CONFIG_PWM_LED_ESP32_LS_CH2_GPIO

GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39.

CONFIG_PWM_LED_ESP32_LS_CH2_TIMER

Timer source channel, allowed values: 0 - 4.

CONFIG_PWM_LED_ESP32_LS_CH3

Enable channel 3

CONFIG_PWM_LED_ESP32_LS_CH3_GPIO

GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39.

CONFIG_PWM_LED_ESP32_LS_CH3_TIMER

Timer source channel, allowed values: 0 - 4.

CONFIG_PWM_LED_ESP32_LS_CH4

Enable channel 4

CONFIG_PWM_LED_ESP32_LS_CH4_GPIO

GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39.

CONFIG_PWM_LED_ESP32_LS_CH4_TIMER

Timer source channel, allowed values: 0 - 4.

CONFIG_PWM_LED_ESP32_LS_CH5

Enable channel 5

CONFIG_PWM_LED_ESP32_LS_CH5_GPIO

GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39.

CONFIG_PWM_LED_ESP32_LS_CH5_TIMER

Timer source channel, allowed values: 0 - 4.

CONFIG_PWM_LED_ESP32_LS_CH6

Enable channel 6

CONFIG_PWM_LED_ESP32_LS_CH6_GPIO

GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39.

CONFIG_PWM_LED_ESP32_LS_CH6_TIMER

Timer source channel, allowed values: 0 - 4.

CONFIG_PWM_LED_ESP32_LS_CH7

Enable channel 7

CONFIG_PWM_LED_ESP32_LS_CH7_GPIO

GPIO number, allowed values: 0 - 19, 21 - 23, 25 - 27 and 32 - 39.

CONFIG_PWM_LED_ESP32_LS_CH7_TIMER

Timer source channel, allowed values: 0 - 4.

CONFIG_PWM_LED_ESP32_LS_TIMER

Set low speed timers

CONFIG_PWM_LED_ESP32_LS_TIMER0

Set timer 0

CONFIG_PWM_LED_ESP32_LS_TIMER0_BIT_NUM

PWM timer precision, allowed values: 10 - 15.

CONFIG_PWM_LED_ESP32_LS_TIMER0_FREQ

Set frequency

CONFIG_PWM_LED_ESP32_LS_TIMER1

Set timer 1

CONFIG_PWM_LED_ESP32_LS_TIMER1_BIT_NUM

PWM timer precision, allowed values: 10 - 15.

CONFIG_PWM_LED_ESP32_LS_TIMER1_FREQ

Set frequency

CONFIG_PWM_LED_ESP32_LS_TIMER2

Set timer 2

CONFIG_PWM_LED_ESP32_LS_TIMER2_BIT_NUM

PWM timer precision, allowed values: 10 - 15.

CONFIG_PWM_LED_ESP32_LS_TIMER2_FREQ

Set frequency

CONFIG_PWM_LED_ESP32_LS_TIMER3

Set timer 3

CONFIG_PWM_LED_ESP32_LS_TIMER3_BIT_NUM

PWM timer precision, allowed values: 10 - 15.

CONFIG_PWM_LED_ESP32_LS_TIMER3_FREQ

Set frequency

CONFIG_PWM_LITEX

Enable support for LiteX PWM driver

CONFIG_PWM_LITEX_INIT_PRIORITY

PWM device driver initialization priority.

CONFIG_PWM_MCUX

Enable mcux pwm driver.

CONFIG_PWM_MCUX_FTM

Enable support for mcux ftm pwm driver.

CONFIG_PWM_NRF5_SW

Enable driver to utilize PWM on the Nordic Semiconductor nRF5x series. This implementation provides up to 3 pins using one HF timer, two PPI channels per pin and one GPIOTE config per pin.

CONFIG_PWM_NRFX

Enable support for nrfx Hardware PWM driver for nRF52 MCU series.

CONFIG_PWM_PCA9685

Enable driver for PCA9685 I2C-based PWM chip.

CONFIG_PWM_PCA9685_0

Enable config options for the PCA9685 I2C-based PWM chip #0.

CONFIG_PWM_PCA9685_0_DEV_NAME

Specify the device name for the PCA9685 I2C-based PWM chip #0.

CONFIG_PWM_PCA9685_0_I2C_ADDR

Specify the I2C slave address for the PCA9685 I2C-based PWM chip #0.

CONFIG_PWM_PCA9685_0_I2C_MASTER_DEV_NAME

Specify the device name of the I2C master device to which this PCA9685 chip #0 is binded.

CONFIG_PWM_PCA9685_INIT_PRIORITY

Device driver initialization priority.

CONFIG_PWM_PWMSWR_LOOP

Loop count for PWM Software Reset when disabling PWM channel.

CONFIG_PWM_RV32M1_TPM

Enable the RV32M1 TPM PWM driver.

CONFIG_PWM_SAM

Enable PWM driver for Atmel SAM MCUs.

CONFIG_PWM_SHELL

Enable the PWM related shell commands.

CONFIG_PWM_SIFIVE

Enable the PWM driver for the SiFive Freedom platform

CONFIG_PWM_SIFIVE_INIT_PRIORITY

SiFive PWM Driver Initialization Priority

CONFIG_PWM_STM32

This option enables the PWM driver for STM32 family of processors. Say y if you wish to use PWM port on STM32 MCU.

CONFIG_PWM_STM32_1

Enable output for PWM1 in the driver. Say y here if you want to use PWM1 output.

CONFIG_PWM_STM32_10

Enable output for PWM10 in the driver. Say y here if you want to use PWM10 output.

CONFIG_PWM_STM32_11

Enable output for PWM11 in the driver. Say y here if you want to use PWM11 output.

CONFIG_PWM_STM32_12

Enable output for PWM12 in the driver. Say y here if you want to use PWM12 output.

CONFIG_PWM_STM32_13

Enable output for PWM13 in the driver. Say y here if you want to use PWM13 output.

CONFIG_PWM_STM32_14

Enable output for PWM14 in the driver. Say y here if you want to use PWM14 output.

CONFIG_PWM_STM32_15

Enable output for PWM15 in the driver. Say y here if you want to use PWM15 output.

CONFIG_PWM_STM32_16

Enable output for PWM16 in the driver. Say y here if you want to use PWM16 output.

CONFIG_PWM_STM32_17

Enable output for PWM17 in the driver. Say y here if you want to use PWM17 output.

CONFIG_PWM_STM32_18

Enable output for PWM18 in the driver. Say y here if you want to use PWM18 output.

CONFIG_PWM_STM32_19

Enable output for PWM19 in the driver. Say y here if you want to use PWM19 output.

CONFIG_PWM_STM32_2

Enable output for PWM2 in the driver. Say y here if you want to use PWM2 output.

CONFIG_PWM_STM32_20

Enable output for PWM20 in the driver. Say y here if you want to use PWM20 output.

CONFIG_PWM_STM32_3

Enable output for PWM3 in the driver. Say y here if you want to use PWM3 output.

CONFIG_PWM_STM32_4

Enable output for PWM4 in the driver. Say y here if you want to use PWM4 output.

CONFIG_PWM_STM32_5

Enable output for PWM5 in the driver. Say y here if you want to use PWM5 output.

CONFIG_PWM_STM32_6

Enable output for PWM6 in the driver. Say y here if you want to use PWM6 output.

CONFIG_PWM_STM32_7

Enable output for PWM7 in the driver. Say y here if you want to use PWM7 output.

CONFIG_PWM_STM32_8

Enable output for PWM8 in the driver. Say y here if you want to use PWM8 output.

CONFIG_PWM_STM32_9

Enable output for PWM9 in the driver. Say y here if you want to use PWM9 output.

CONFIG_PWM_XEC

Enable driver to utilize PWM on the Microchip XEC IP block.

CONFIG_QDEC_NRFX

Enable support for nrfx QDEC driver for nRF MCU series.

CONFIG_QEMU_TICKLESS_WORKAROUND

Qemu (without -icount) has trouble keeping time when the host process needs to timeshare. The host OS will routinely schedule out a process at timescales equivalent to the guest tick rate. With traditional ticks delivered regularly by the hardware, that’s mostly OK as it looks like a late interrupt. But in tickless mode, the driver needs some CPU in order to schedule the tick in the first place. If that gets delayed across a tick boundary, time gets wonky. This tunable is a hint to the driver to disable tickless accounting on qemu. Use it only on tests that are known to have problems.

CONFIG_RAM_CONSOLE

Emit console messages to a RAM buffer “ram_console” which can be examined at runtime with a debugger. Useful in board bring-up if there aren’t any working serial drivers.

CONFIG_RAM_CONSOLE_BUFFER_SIZE

Size of the RAM console buffer. Messages will wrap around if the length is exceeded.

CONFIG_RISCV_MACHINE_TIMER

This module implements a kernel device driver for the generic RISCV machine timer driver. It provides the standard “system clock driver” interfaces.

CONFIG_RTT_CONSOLE

Emit console messages to a RAM buffer that is then read by the Segger J-Link software and displayed on a computer in real-time. Requires support for Segger J-Link on the companion IC onboard.

CONFIG_RTT_TX_RETRY_CNT

Number of TX retries before dropping the byte and assuming that RTT session is inactive.

CONFIG_RTT_TX_RETRY_DELAY_MS

Sleep period between TX retry attempts. During RTT session, host pulls data periodically. Period starts from 1-2 milliseconds and can be increased if traffic on RTT increases (also from host to device). In case of heavy traffic data can be lost and it may be necessary to increase delay or number of retries.

CONFIG_RTT_TX_RETRY_IN_INTERRUPT

If enabled RTT console will busy wait between TX retries when console assumes that RTT session is active. In case of heavy traffic data can be lost and it may be necessary to increase delay or number of retries.

CONFIG_RV32M1_INTMUX

Select this option to enable support for the RV32M1 INTMUX driver. This provides a level 2 interrupt controller for the SoC. The INTMUX peripheral combines level 2 interrupts into eight channels; each channel has its own level 1 interrupt to the core.

CONFIG_RV32M1_INTMUX_CHANNEL_0

Enable support for INTMUX channel 0.

CONFIG_RV32M1_INTMUX_CHANNEL_1

Enable support for INTMUX channel 1.

CONFIG_RV32M1_INTMUX_CHANNEL_2

Enable support for INTMUX channel 2.

CONFIG_RV32M1_INTMUX_CHANNEL_3

Enable support for INTMUX channel 3.

CONFIG_RV32M1_INTMUX_CHANNEL_4

Enable support for INTMUX channel 4.

CONFIG_RV32M1_INTMUX_CHANNEL_5

Enable support for INTMUX channel 5.

CONFIG_RV32M1_INTMUX_CHANNEL_6

Enable support for INTMUX channel 6.

CONFIG_RV32M1_INTMUX_CHANNEL_7

Enable support for INTMUX channel 7.

CONFIG_RV32M1_INTMUX_INIT_PRIORITY

Boot time initialization priority for INTMUX driver. Don’t change the default unless you know what you are doing.

CONFIG_RV32M1_LPTMR_TIMER

This module implements a kernel device driver for using the LPTMR peripheral as the system clock. It provides the standard “system clock driver” interfaces.

CONFIG_SAM0_EIC

Enable EIC driver for SAM0 series of devices. This is required for GPIO interrupt support.

CONFIG_SAM0_RTC_TIMER

This module implements a kernel device driver for the Atmel SAM0 series Real Time Counter and provides the standard “system clock driver” interfaces.

CONFIG_SDL_DISPLAY

Enable SDL based emulated display compliant with display driver API.

CONFIG_SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_ARGB_8888

ARGB 8888

CONFIG_SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_BGR_565

BGR 565

CONFIG_SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_MONO01

Mono Black=0

CONFIG_SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_MONO10

Mono Black=1

CONFIG_SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_RGB_565

RGB 565

CONFIG_SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_RGB_888

RGB 888

CONFIG_SDL_DISPLAY_DEV_NAME

SDL display device name

CONFIG_SDL_DISPLAY_X_RES

X resolution for SDL display

CONFIG_SDL_DISPLAY_Y_RES

Y resolution for SDL display

CONFIG_SENSOR

Include sensor drivers in config

CONFIG_SENSOR_INIT_PRIORITY

Sensor initialization priority.

CONFIG_SENSOR_SHELL

This shell provides access to basic sensor data.

CONFIG_SERIAL

Enable options for serial drivers.

CONFIG_SERIAL_HAS_DRIVER

This is an option to be enabled by individual serial driver to signal that there is a serial driver. This is being used by other drivers which are dependent on serial.

CONFIG_SERIAL_SUPPORT_ASYNC

This is an option to be enabled by individual serial driver to signal that the driver and hardware supports async operation.

CONFIG_SERIAL_SUPPORT_INTERRUPT

This is an option to be enabled by individual serial driver to signal that the driver and hardware supports interrupts.

CONFIG_SHARED_IRQ

Include shared interrupt support in system. Shared interrupt support is NOT required in most systems. If in doubt answer no.

CONFIG_SHARED_IRQ_0

Provide an instance of the shared interrupt driver when system configuration requires that multiple devices share an interrupt.

CONFIG_SHARED_IRQ_1

Provide an instance of the shared interrupt driver when system configuration requires that multiple devices share an interrupt.

CONFIG_SHARED_IRQ_INIT_PRIORITY

Shared IRQ are initialized on POST_KERNEL init level. They have to be initialized before any device that uses them.

CONFIG_SHARED_IRQ_NUM_CLIENTS

Configures the maximum number of clients allowed per shared instance of the shared interrupt driver. To conserve RAM set this value to the lowest practical value.

CONFIG_SHT3XD

Enable driver for SHT3xD temperature and humidity sensors.

CONFIG_SHT3XD_MPS_05

0.5

CONFIG_SHT3XD_MPS_1

1

CONFIG_SHT3XD_MPS_10

10

CONFIG_SHT3XD_MPS_2

2

CONFIG_SHT3XD_MPS_4

4

CONFIG_SHT3XD_PERIODIC_MODE

periodic data acquisition

CONFIG_SHT3XD_REPEATABILITY_HIGH

high

CONFIG_SHT3XD_REPEATABILITY_LOW

low

CONFIG_SHT3XD_REPEATABILITY_MEDIUM

medium

CONFIG_SHT3XD_SINGLE_SHOT_MODE

single shot

CONFIG_SHT3XD_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_SHT3XD_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_SHT3XD_TRIGGER

CONFIG_SHT3XD_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_SHT3XD_TRIGGER_NONE

No trigger

CONFIG_SHT3XD_TRIGGER_OWN_THREAD

Use own thread

CONFIG_SI7006

Enable I2C-based driver for Si7006 Temperature and Humidity Sensor.

CONFIG_SI7060

Enable driver for SI7060 temperature sensors.

CONFIG_SIFIVE_SPI_0_ROM

If enabled, SPI 0 is reserved for accessing the SPI flash ROM and a driver interface won’t be instantiated for SPI 0.

Beware disabling this option on HiFive 1! The SPI flash ROM is where the program is stored, and if this driver initializes the interface for peripheral control the FE310 will crash on boot.

CONFIG_SLIP

SLIP driver

CONFIG_SLIP_DRV_NAME

This option sets the driver name

CONFIG_SLIP_MAC_ADDR

Specify a MAC address for the SLIP interface in the form of six hex 8-bit chars separated by colons (e.g.: aa:33:cc:22:e2:c0). The default is an empty string, which means the code will make 00:00:5E:00:53:XX, where XX will be random.

CONFIG_SLIP_STATISTICS

This option enables statistics support for SLIP driver.

CONFIG_SLIP_TAP

In TAP the Ethernet frames are transferred over SLIP.

CONFIG_SOC_FLASH_GECKO

Enable Silicon Labs Gecko series internal flash driver.

CONFIG_SOC_FLASH_MCUX

Enables the MCUX flash shim driver. WARNING: This driver will disable the system interrupts for the duration of the flash erase/write operations. This will have an impact on the overall system performance - whether this is acceptable or not will depend on the use case.

CONFIG_SOC_FLASH_NIOS2_QSPI

Enables the Nios-II QSPI flash driver.

CONFIG_SOC_FLASH_NIOS2_QSPI_DEV_NAME

Specify the device name for the QSPI flash driver.

CONFIG_SOC_FLASH_NRF

Enables Nordic Semiconductor nRF flash driver.

CONFIG_SOC_FLASH_NRF_EMULATE_ONE_BYTE_WRITE_ACCESS

When this option is enabled writing chunks less than minimal write block size parameter (imposed by manufacturer) is possible but operation is more complex and requires basic user knowledge about NVMC controller.

CONFIG_SOC_FLASH_NRF_RADIO_SYNC

Enable synchronization between flash memory driver and radio.

CONFIG_SOC_FLASH_NRF_UICR

Enable operations on UICR. Once enabled UICR are written or read as ordinary flash memory. Erase is possible for whole UICR at once.

CONFIG_SOC_FLASH_RV32M1

Enables the RV32M1 flash shim driver. WARNING: This driver will disable the system interrupts for the duration of the flash erase/write operations. This will have an impact on the overall system performance - whether this is acceptable or not will depend on the use case.

CONFIG_SOC_FLASH_SAM

Enable the Atmel SAM series internal flash driver.

CONFIG_SOC_FLASH_SAM0

Enable the Atmel SAM0 series internal flash driver.

CONFIG_SOC_FLASH_SAM0_EMULATE_BYTE_PAGES

Emulate a device with byte-sized pages by doing a read/modify/erase/write.

CONFIG_SOC_FLASH_STM32

Enable STM32F0x, STM32F3x, STM32F4x, STM32F7x, STM32L4x, STM32WBx, STM32G0x or STM32G4x series flash driver.

CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58

Allow enabling the nRF SPI Master with EasyDMA, despite Product Anomaly Notice 58 (SPIM: An additional byte is clocked out when RXD.MAXCNT == 1 and TXD.MAXCNT <= 1). Without this override, the SPI Master is only available without EasyDMA. Note that the ‘SPIM’ and ‘SPIS’ drivers use EasyDMA, while the ‘SPI’ driver does not. Use this option ONLY if you are certain that transactions with RXD.MAXCNT == 1 and TXD.MAXCNT <= 1 will NOT be executed.

CONFIG_SPI

Enable support for the SPI hardware bus.

CONFIG_SPI_0

Enable SPI controller port 0.

CONFIG_SPI_0_NRF_ORC

Over-read character. Character clocked out after an over-read of the transmit buffer.

CONFIG_SPI_0_NRF_SPI

Enable nRF SPI Master without EasyDMA on port 0.

CONFIG_SPI_0_NRF_SPIM

Enable nRF SPI Master with EasyDMA on port 0.

CONFIG_SPI_0_NRF_SPIS

Enable nRF SPI Slave with EasyDMA on port 0. Due to hardware limitations the implementation supports only simple buffers (consisting of one part) located in RAM.

CONFIG_SPI_0_OP_MODES

This sets the supported operation modes at runtime, by the SPI port 0, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available.

CONFIG_SPI_1

Enable SPI controller port 1.

CONFIG_SPI_1_NRF_ORC

Over-read character. Character clocked out after an over-read of the transmit buffer.

CONFIG_SPI_1_NRF_SPI

Enable nRF SPI Master without EasyDMA on port 1.

CONFIG_SPI_1_NRF_SPIM

Enable nRF SPI Master with EasyDMA on port 1.

CONFIG_SPI_1_NRF_SPIS

Enable nRF SPI Slave with EasyDMA on port 1. Due to hardware limitations the implementation supports only simple buffers (consisting of one part) located in RAM.

CONFIG_SPI_1_OP_MODES

This sets the supported operation modes at runtime, by the SPI port 1, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available.

CONFIG_SPI_2

Enable SPI controller port 2.

CONFIG_SPI_2_NRF_ORC

Over-read character. Character clocked out after an over-read of the transmit buffer.

CONFIG_SPI_2_NRF_SPI

Enable nRF SPI Master without EasyDMA on port 2.

CONFIG_SPI_2_NRF_SPIM

Enable nRF SPI Master with EasyDMA on port 2.

CONFIG_SPI_2_NRF_SPIS

Enable nRF SPI Slave with EasyDMA on port 2. Due to hardware limitations the implementation supports only simple buffers (consisting of one part) located in RAM.

CONFIG_SPI_2_OP_MODES

This sets the supported operation modes at runtime, by the SPI port 2, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available.

CONFIG_SPI_3

Enable SPI controller port 3.

CONFIG_SPI_3_NRF_ORC

Over-read character. Character clocked out after an over-read of the transmit buffer.

CONFIG_SPI_3_NRF_RX_DELAY

Number of 64 MHz clock cycles (15.625 ns) delay from the sampling edge of SCK (leading or trailing, depending on the CPHA setting used) until the input serial data on MISO is actually sampled.

CONFIG_SPI_3_NRF_SPIM

Enable nRF SPI Master with EasyDMA on port 3.

CONFIG_SPI_3_NRF_SPIS

Enable nRF SPI Slave with EasyDMA on port 3. Due to hardware limitations the implementation supports only simple buffers (consisting of one part) located in RAM.

CONFIG_SPI_3_OP_MODES

This sets the supported operation modes at runtime, by the SPI port 3, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available.

CONFIG_SPI_4

Enable SPI controller port 4.

CONFIG_SPI_4_NRF_ORC

Over-read character. Character clocked out after an over-read of the transmit buffer.

CONFIG_SPI_4_NRF_RX_DELAY

Number of 64 MHz clock cycles (15.625 ns) delay from the sampling edge of SCK (leading or trailing, depending on the CPHA setting used) until the input serial data on MISO is actually sampled.

CONFIG_SPI_4_NRF_SPIM

Enable nRF SPI Master with EasyDMA on port 4.

CONFIG_SPI_4_OP_MODES

This sets the supported operation modes at runtime, by the SPI port 4, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available.

CONFIG_SPI_5

Enable SPI controller port 5.

CONFIG_SPI_5_OP_MODES

This sets the supported operation modes at runtime, by the SPI port 5, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available.

CONFIG_SPI_6

Enable SPI controller port 6.

CONFIG_SPI_6_OP_MODES

This sets the supported operation modes at runtime, by the SPI port 6, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available.

CONFIG_SPI_7

Enable SPI controller port 7.

CONFIG_SPI_7_OP_MODES

This sets the supported operation modes at runtime, by the SPI port 7, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available.

CONFIG_SPI_8

Enable SPI controller port 8.

CONFIG_SPI_8_OP_MODES

This sets the supported operation modes at runtime, by the SPI port 8, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available.

CONFIG_SPI_ASYNC

This option enables the asynchronous API calls.

CONFIG_SPI_CC13XX_CC26XX

Enable support for the TI SimpleLink CC13xx / CC26xx SPI peripheral

CONFIG_SPI_DW

Enable support for Designware’s SPI controllers.

CONFIG_SPI_DW_ACCESS_WORD_ONLY

In some case, e.g. ARC HS Development kit, the peripheral space of DesignWare SPI only allows word access, byte access will raise exception.

CONFIG_SPI_DW_ARC_AUX_REGS

SPI IP block registers are part of user extended auxiliary registers and thus their access is different than memory mapped registers.

CONFIG_SPI_DW_FIFO_DEPTH

Corresponds to the SSI_TX_FIFO_DEPTH and SSI_RX_FIFO_DEPTH of the DesignWare Synchronous Serial Interface. Depth ranges from 2-256.

CONFIG_SPI_DW_PORT_0_CLOCK_GATE

Enable clock gating

CONFIG_SPI_DW_PORT_0_CLOCK_GATE_DRV_NAME

CONFIG_SPI_DW_PORT_0_CLOCK_GATE_SUBSYS

Clock controller’s subsystem

CONFIG_SPI_DW_PORT_0_INTERRUPT_SINGLE_LINE

Only one line is used to trigger interrupts: RX, TX and ERROR interrupt go all through that line, undifferentiated.

CONFIG_SPI_DW_PORT_1_CLOCK_GATE

Enable clock gating

CONFIG_SPI_DW_PORT_1_CLOCK_GATE_DRV_NAME

CONFIG_SPI_DW_PORT_1_CLOCK_GATE_SUBSYS

Clock controller’s subsystem

CONFIG_SPI_DW_PORT_1_INTERRUPT_SINGLE_LINE

Single interrupt line for all interrupts

CONFIG_SPI_DW_PORT_2_CLOCK_GATE

Enable clock gating

CONFIG_SPI_DW_PORT_2_CLOCK_GATE_DRV_NAME

CONFIG_SPI_DW_PORT_2_CLOCK_GATE_SUBSYS

Clock controller’s subsystem

CONFIG_SPI_DW_PORT_2_INTERRUPT_SINGLE_LINE

Only one line is used to trigger interrupts: RX, TX and ERROR interrupt go all through that line, undifferentiated.

CONFIG_SPI_DW_PORT_3_CLOCK_GATE

Enable clock gating

CONFIG_SPI_DW_PORT_3_CLOCK_GATE_DRV_NAME

CONFIG_SPI_DW_PORT_3_CLOCK_GATE_SUBSYS

Clock controller’s subsystem

CONFIG_SPI_DW_PORT_3_INTERRUPT_SINGLE_LINE

Only one line is used to trigger interrupts: RX, TX and ERROR interrupt go all through that line, undifferentiated.

CONFIG_SPI_FLASH_W25QXXDV

SPI NOR Flash Winbond W25QXXDV

CONFIG_SPI_FLASH_W25QXXDV_DEVICE_ID

This is the device ID of the flash chip to use, which is 0x00ef4015 for the W25QXXDV

CONFIG_SPI_FLASH_W25QXXDV_DRV_NAME

SPI flash device name

CONFIG_SPI_FLASH_W25QXXDV_FLASH_SIZE

This is the flash capacity in bytes.

CONFIG_SPI_FLASH_W25QXXDV_GPIO_CS_WAIT_DELAY

This is the wait delay (in us) to allow for CS switching to take effect

CONFIG_SPI_FLASH_W25QXXDV_GPIO_SPI_CS

This option is useful if one needs to manage SPI CS through a GPIO pin to by-pass the SPI controller’s CS logic.

CONFIG_SPI_FLASH_W25QXXDV_INIT_PRIORITY

Device driver initialization priority. Device is connected to SPI bus, it has to be initialized after SPI driver.

CONFIG_SPI_FLASH_W25QXXDV_PAGE_PROGRAM_SIZE

This is the maximum size of a page program operation. Writing data over this page boundary will split the write operation into two pages.

CONFIG_SPI_GECKO

Enable the SPI peripherals on Gecko

CONFIG_SPI_INIT_PRIORITY

Device driver initialization priority.

CONFIG_SPI_LITESPI

Enable the SPI peripherals on LiteX

CONFIG_SPI_MCUX_DSPI

Enable support for mcux spi driver.

CONFIG_SPI_MCUX_FLEXCOMM

Enable support for mcux flexcomm spi driver.

CONFIG_SPI_MCUX_LPSPI

Enable support for mcux spi driver.

CONFIG_SPI_NOR

SPI NOR Flash

CONFIG_SPI_NOR_CS_WAIT_DELAY

This is the wait delay (in us) to allow for CS switching to take effect

CONFIG_SPI_NOR_FLASH_LAYOUT_PAGE_SIZE

When CONFIG_FLASH_PAGE_LAYOUT is used this driver will support that API. By default the page size corresponds to the block size (65536). Other options include the 32K-byte erase size (32768), the sector size (4096), or any non-zero multiple of the sector size.

CONFIG_SPI_NOR_IDLE_IN_DPD

Where supported deep power-down mode can reduce current draw to as little as 0.1% of standby current. However it takes some milliseconds to enter and exit from this mode.

Select this option for applications where device power management is not enabled, the flash remains inactive for long periods, and when used the impact of waiting for mode enter and exit delays is acceptable.

CONFIG_SPI_NOR_INIT_PRIORITY

Device driver initialization priority. Device is connected to SPI bus, it has to be initialized after SPI driver.

CONFIG_SPI_NRFX

Enable support for nrfx SPI drivers for nRF MCU series. Peripherals with the same instance ID cannot be used together, e.g. SPI_0 and I2C_0. You may need to disable I2C_0 or I2C_1.

CONFIG_SPI_NRFX_RAM_BUFFER_SIZE

SPIM peripherals cannot transmit data directly from flash. Therefore, a buffer in RAM needs to be provided for each instance of SPI driver using SPIM peripheral, so that the driver can copy there a chunk of data from flash and transmit it. The size is specified in bytes. A size of 0 means that this feature should be disabled, and the application must then take care of not supplying buffers located in flash to the driver, otherwise such transfers will fail.

CONFIG_SPI_OC_SIMPLE

Enable the Simple SPI controller

CONFIG_SPI_OC_SIMPLE_BUS_WIDTH

CONFIG_SPI_RV32M1_LPSPI

Enable the RV32M1 LPSPI driver.

CONFIG_SPI_SAM

Enable support for the SAM SPI driver.

CONFIG_SPI_SAM0

Enable support for the SAM0 SERCOM SPI driver.

CONFIG_SPI_SAME70_PORT_0_PIN_CS0

CS0 pin

CONFIG_SPI_SAME70_PORT_0_PIN_CS1_PA31

PA31

CONFIG_SPI_SAME70_PORT_0_PIN_CS1_PD25

PD25

CONFIG_SPI_SAME70_PORT_0_PIN_CS2

CS2 pin

CONFIG_SPI_SAME70_PORT_0_PIN_CS3

CS3 pin

CONFIG_SPI_SAME70_PORT_1_PIN_CS0

CS0 pin

CONFIG_SPI_SAME70_PORT_1_PIN_CS1_PC28

PC28

CONFIG_SPI_SAME70_PORT_1_PIN_CS1_PD0

PD0

CONFIG_SPI_SAME70_PORT_1_PIN_CS2_PC29

PC29

CONFIG_SPI_SAME70_PORT_1_PIN_CS2_PD1

PD1

CONFIG_SPI_SAME70_PORT_1_PIN_CS3_PC30

PC30

CONFIG_SPI_SAME70_PORT_1_PIN_CS3_PD2

PD2

CONFIG_SPI_SAM_PORT_0

Enable SPI0 at boot

CONFIG_SPI_SAM_PORT_1

Enable SPI1 at boot

CONFIG_SPI_SIFIVE

Enable the SPI peripherals on SiFive Freedom processors

CONFIG_SPI_SLAVE

Enables Driver SPI slave operations. Slave support depends on the driver and the hardware it runs on.

CONFIG_SPI_STM32

Enable SPI support on the STM32 family of processors.

CONFIG_SPI_STM32_HAS_FIFO

CONFIG_SPI_STM32_INTERRUPT

Enable Interrupt support for the SPI Driver of STM32 family.

CONFIG_SPI_STM32_USE_HW_SS

Use Slave Select pin instead of software Slave Select.

CONFIG_SPI_XEC_QMSPI

Enable support for the Microchip XEC QMSPI driver.

CONFIG_SSD1306

Enable driver for SSD1306 display driver.

CONFIG_SSD1306_DEFAULT

Default SSD1306 controller

CONFIG_SSD1306_DEFAULT_CONTRAST

SSD16XX default contrast.

CONFIG_SSD1306_REVERSE_MODE

SSD16XX reverse video mode.

CONFIG_SSD1306_SH1106_COMPATIBLE

Enable SH1106 compatible mode

CONFIG_SSD16XX

Enable driver for SSD16XX compatible controller.

CONFIG_ST7789V

Enable driver for ST7789V display driver.

CONFIG_ST7789V_RGB565

RGB565

CONFIG_ST7789V_RGB888

RGB888

CONFIG_STM32_LPTIM_CLOCK

LPTIM clock value

CONFIG_STM32_LPTIM_CLOCK_LSE

Use LSE as LPTIM clock

CONFIG_STM32_LPTIM_CLOCK_LSI

Use LSI as LPTIM clock

CONFIG_STM32_LPTIM_TIMEBASE

LPTIM AutoReload value

CONFIG_STM32_LPTIM_TIMER

This module implements a kernel device driver for the LowPower Timer and provides the standard “system clock driver” interfaces.

CONFIG_STTS751

Enable driver for STTS751 I2C-based temperature sensor.

CONFIG_STTS751_SAMPLING_RATE

Sensor output data rate expressed in conversions per second. Data rates supported by the chip are: 0: 1 conv every 16 sec 1: 1 conv every 8 sec 2: 1 conv every 4 sec 3: 1 conv every 2 sec 4: 1 conv every sec 5: 2 convs every sec 6: 4 convs every sec 7: 8 convs every sec 8: 16 convs every sec 9: 32 convs every sec

CONFIG_STTS751_TEMP_HI_THRESHOLD

HIGH temperature threshold to trigger an alarm

CONFIG_STTS751_TEMP_LO_THRESHOLD

LOW temperature threshold to trigger an alarm

CONFIG_STTS751_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_STTS751_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_STTS751_TRIGGER

CONFIG_STTS751_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_STTS751_TRIGGER_NONE

No trigger

CONFIG_STTS751_TRIGGER_OWN_THREAD

Use own thread

CONFIG_SWERV_PIC

Programmable Interrupt Controller for the SweRV EH1 RISC-V CPU;

CONFIG_SX9500

Enable driver for SX9500 I2C-based SAR proximity sensor.

CONFIG_SX9500_PROX_CHANNEL

The SX9500 offers 4 separate proximity channels. Choose which one you are using. Valid numbers are 0 to 3.

CONFIG_SX9500_THREAD_PRIORITY

Thread priority

CONFIG_SX9500_THREAD_STACK_SIZE

Sensor delayed work thread stack size

CONFIG_SX9500_TRIGGER

CONFIG_SX9500_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_SX9500_TRIGGER_NONE

No trigger

CONFIG_SX9500_TRIGGER_OWN_THREAD

Use own thread

CONFIG_SYSTEM_CLOCK_DISABLE

This option enables the sys_clock_disable() API in the kernel. It is needed by some subsystems (which will automatically select it), but is rarely needed by applications.

CONFIG_SYSTEM_CLOCK_INIT_PRIORITY

This options can be used to set a specific initialization priority value for the system clock driver. As driver initialization might need the clock to be running already, you should let the default value as it is (0).

CONFIG_SYSTEM_CLOCK_SLOPPY_IDLE

When true, the timer driver is not required to maintain a correct system uptime count when the system enters idle. Some platforms may take advantage of this to reduce the overhead from regular interrupts required to handle counter wraparound conditions.

CONFIG_TEMP_KINETIS

Enable driver for NXP Kinetis temperature sensor.

CONFIG_TEMP_KINETIS_OVERSAMPLING

ADC oversampling to use for the temperature sensor and bandgap voltage readings. Oversampling can help in providing more stable readings.

CONFIG_TEMP_KINETIS_RESOLUTION

ADC resolution to use for the temperature sensor and bandgap voltage readings.

CONFIG_TEMP_NRF5

Enable driver for nRF5 temperature sensor.

CONFIG_TH02

Enable driver for the TH02 temperature sensor.

CONFIG_TICKLESS_CAPABLE

Timer drivers should select this flag if they are capable of supporting tickless operation. That is, a call to z_clock_set_timeout() with a number of ticks greater than one should be expected not to produce a call to z_clock_announce() (really, not to produce an interrupt at all) until the specified expiration.

CONFIG_TIMER_DTMR_CMSDK_APB

The dualtimer (DTMR) present in the platform is used as a timer. This option enables the support for the timer.

CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME

The drivers select this option automatically when needed. Do not modify this unless you have a very good reason for it.

CONFIG_TIMER_TMR_CMSDK_APB

The timers (TMR) present in the platform are used as timers. This option enables the support for the timers.

CONFIG_TI_HDC

Enable driver for TI temperature and humidity sensors.

CONFIG_TMP007

Enable driver for TMP007 infrared thermopile sensors.

CONFIG_TMP007_THREAD_PRIORITY

Priority of thread used by the driver to handle interrupts.

CONFIG_TMP007_THREAD_STACK_SIZE

Stack size of thread used by the driver to handle interrupts.

CONFIG_TMP007_TRIGGER

CONFIG_TMP007_TRIGGER_GLOBAL_THREAD

Use global thread

CONFIG_TMP007_TRIGGER_NONE

No trigger

CONFIG_TMP007_TRIGGER_OWN_THREAD

Use own thread

CONFIG_TMP112

Enable the driver for Texas Instruments TMP112 High-Accuracy Digital Temperature Sensors.

The TMP102 is compatible with the TMP112 but is less accurate and has been successfully tested with this driver.

CONFIG_TMP116

Enable driver for TMP116 temperature sensor.

CONFIG_TSC_CYCLES_PER_SEC

The x86 implementation of LOAPIC k_cycle_get_32() relies on the x86 TSC. This runs at the CPU speed and not the bus speed. If set to 0, the value of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC will be used instead; many MCUs these values are the same.

CONFIG_UARTE_NRF_HW_ASYNC

CONFIG_UART_0_ASYNC

This option enables UART Asynchronous API support on port 0.

CONFIG_UART_0_GPIO_MANAGEMENT

If enabled, the driver will configure the GPIOs used by the uart to their default configuration when device is powered down. The GPIOs will be configured back to correct state when UART is powered up.

CONFIG_UART_0_INTERRUPT_DRIVEN

This option enables UART interrupt support on port 0.

CONFIG_UART_0_NRF_FLOW_CONTROL

Enable flow control. If selected, additionally two pins, RTS and CTS have to be configured.

CONFIG_UART_0_NRF_HW_ASYNC

If default driver uses interrupts to count incoming bytes, it is possible that with higher speeds and/or high cpu load some data can be lost. It is recommended to use hardware byte counting in such scenarios. Hardware RX byte counting requires timer instance and one PPI channel

CONFIG_UART_0_NRF_HW_ASYNC_TIMER

Timer instance

CONFIG_UART_0_NRF_PARITY_BIT

Enable parity bit.

CONFIG_UART_0_NRF_TX_BUFFER_SIZE

Size of the transmit buffer for API function: fifo_fill. This value is limited by range of TXD.MAXCNT register for particular SoC.

CONFIG_UART_0_NRF_UART

Enable nRF UART without EasyDMA on port 0.

CONFIG_UART_0_NRF_UARTE

Enable nRF UART with EasyDMA on port 0.

CONFIG_UART_1

Enable support for USART1 port in the driver. Say y here if you want to use USART1 device.

CONFIG_UART_10

Enable support for UART10 port in the driver. Say y here if you want to use UART10 device.

CONFIG_UART_1_ASYNC

This option enables UART Asynchronous API support on port 1.

CONFIG_UART_1_GPIO_MANAGEMENT

If enabled, the driver will configure the GPIOs used by the uart to their default configuration when device is powered down. The GPIOs will be configured back to correct state when UART is powered up.

CONFIG_UART_1_INTERRUPT_DRIVEN

This option enables UART interrupt support on port 1.

CONFIG_UART_1_NRF_FLOW_CONTROL

Enable flow control. If selected, additionally two pins, RTS and CTS have to be configured.

CONFIG_UART_1_NRF_HW_ASYNC

If default driver uses interrupts to count incoming bytes, it is possible that with higher speeds and/or high cpu load some data can be lost. It is recommended to use hardware byte counting in such scenarios. Hardware RX byte counting requires timer instance and one PPI channel

CONFIG_UART_1_NRF_HW_ASYNC_TIMER

Timer instance

CONFIG_UART_1_NRF_PARITY_BIT

Enable parity bit.

CONFIG_UART_1_NRF_TX_BUFFER_SIZE

Size of the transmit buffer for API function: fifo_fill. This value is limited by range of TXD.MAXCNT register for particular SoC.

CONFIG_UART_1_NRF_UARTE

Enable nRF UART with EasyDMA on port 1.

CONFIG_UART_2

Enable support for USART2 port in the driver. Say y here if you want to use USART2 device.

CONFIG_UART_2_ASYNC

This option enables UART Asynchronous API support on port 2.

CONFIG_UART_2_GPIO_MANAGEMENT

If enabled, the driver will configure the GPIOs used by the uart to their default configuration when device is powered down. The GPIOs will be configured back to correct state when UART is powered up.

CONFIG_UART_2_INTERRUPT_DRIVEN

This option enables UART interrupt support on port 2.

CONFIG_UART_2_NRF_FLOW_CONTROL

Enable flow control. If selected, additionally two pins, RTS and CTS have to be configured.

CONFIG_UART_2_NRF_HW_ASYNC

If default driver uses interrupts to count incoming bytes, it is possible that with higher speeds and/or high cpu load some data can be lost. It is recommended to use hardware byte counting in such scenarios. Hardware RX byte counting requires timer instance and one PPI channel

CONFIG_UART_2_NRF_HW_ASYNC_TIMER

Timer instance

CONFIG_UART_2_NRF_PARITY_BIT

Enable parity bit.

CONFIG_UART_2_NRF_TX_BUFFER_SIZE

Size of the transmit buffer for API function: fifo_fill. This value is limited by range of TXD.MAXCNT register for particular SoC.

CONFIG_UART_2_NRF_UARTE

Enable nRF UART with EasyDMA on port 2.

CONFIG_UART_3

Enable support for USART3 port in the driver. Say y here if you want to use USART3 device.

CONFIG_UART_3_ASYNC

This option enables UART Asynchronous API support on port 3.

CONFIG_UART_3_GPIO_MANAGEMENT

If enabled, the driver will configure the GPIOs used by the uart to their default configuration when device is powered down. The GPIOs will be configured back to correct state when UART is powered up.

CONFIG_UART_3_INTERRUPT_DRIVEN

This option enables UART interrupt support on port 3.

CONFIG_UART_3_NRF_FLOW_CONTROL

Enable flow control. If selected, additionally two pins, RTS and CTS have to be configured.

CONFIG_UART_3_NRF_HW_ASYNC

If default driver uses interrupts to count incoming bytes, it is possible that with higher speeds and/or high cpu load some data can be lost. It is recommended to use hardware byte counting in such scenarios. Hardware RX byte counting requires timer instance and one PPI channel

CONFIG_UART_3_NRF_HW_ASYNC_TIMER

Timer instance

CONFIG_UART_3_NRF_PARITY_BIT

Enable parity bit.

CONFIG_UART_3_NRF_TX_BUFFER_SIZE

Size of the transmit buffer for API function: fifo_fill. This value is limited by range of TXD.MAXCNT register for particular SoC.

CONFIG_UART_3_NRF_UARTE

Enable nRF UART with EasyDMA on port 3.

CONFIG_UART_4

Enable support for U(S)ART4 port in the driver. Say y here if you want to use U(S)ART4 device.

CONFIG_UART_5

Enable support for U(S)ART5 port in the driver. Say y here if you want to use U(S)ART5 device.

CONFIG_UART_6

Enable support for USART6 port in the driver. Say y here if you want to use USART6 device.

CONFIG_UART_7

Enable support for U(S)ART7 port in the driver. Say y here if you want to use U(S)ART7 device.

CONFIG_UART_8

Enable support for U(S)ART8 port in the driver. Say y here if you want to use U(S)ART8 device.

CONFIG_UART_9

Enable support for UART9 port in the driver. Say y here if you want to use UART9 device.

CONFIG_UART_ALTERA_JTAG

Enable the Altera JTAG UART driver, built in to many Nios II CPU designs.

CONFIG_UART_ASYNC_API

This option enables new asynchronous UART API.

CONFIG_UART_CC13XX_CC26XX

Enable the TI SimpleLink CC13xx / CC26xx UART driver.

CONFIG_UART_CC13XX_CC26XX_0

Enable UART 0.

CONFIG_UART_CC13XX_CC26XX_1

Enable UART 1.

CONFIG_UART_CC32XX

This option enables the CC32XX UART driver, for UART_0.

CONFIG_UART_CMSDK_APB

This option enables the UART driver for ARM CMSDK APB UART.

CONFIG_UART_CONSOLE

Enable this option to use one UART for console. Make sure CONFIG_UART_CONSOLE_ON_DEV_NAME is also set correctly.

CONFIG_UART_CONSOLE_DEBUG_SERVER_HOOKS

This option allows a debug server agent such as GDB to take over the handling of traffic that goes through the console logic. The debug server looks at characters received and decides to handle them itself if they are some sort of control characters, or let the regular console code handle them if they are of no special significance to it.

CONFIG_UART_CONSOLE_INIT_PRIORITY

Device driver initialization priority. Console has to be initialized after the UART driver it uses.

CONFIG_UART_CONSOLE_MCUMGR

Enables the UART console to receive mcumgr frames for image upgrade and device management. When enabled, the UART console does not process mcumgr frames, but it hands them up to a higher level module (e.g., the shell). If unset, incoming mcumgr frames are dropped.

CONFIG_UART_CONSOLE_ON_DEV_NAME

This option specifies the name of UART device to be used for UART console.

CONFIG_UART_DRV_CMD

This enables the API to send extra commands to drivers. This allows drivers to expose hardware specific functions.

Says no if not sure.

CONFIG_UART_ESP32

Enable the ESP32 UART using ROM routines.

CONFIG_UART_GECKO

Enable the Gecko uart driver.

CONFIG_UART_IMX

This option enables the UART driver for NXP i.MX7 family processors.

CONFIG_UART_IMX_UART_1

Enable support for UART1 port in the driver. Say y here if you want to use UART1 device.

CONFIG_UART_IMX_UART_2

Enable support for UART2 port in the driver. Say y here if you want to use UART2 device.

CONFIG_UART_IMX_UART_3

Enable support for UART3 port in the driver. Say y here if you want to use UART3 device.

CONFIG_UART_IMX_UART_4

Enable support for UART4 port in the driver. Say y here if you want to use UART4 device.

CONFIG_UART_IMX_UART_5

Enable support for UART5 port in the driver. Say y here if you want to use UART5 device.

CONFIG_UART_IMX_UART_6

Enable support for UART6 port in the driver. Say y here if you want to use UART6 device.

CONFIG_UART_IMX_UART_7

Enable support for UART7 port in the driver. Say y here if you want to use UART7 device.

CONFIG_UART_INTERRUPT_DRIVEN

This option enables interrupt support for UART allowing console input and other UART based drivers.

CONFIG_UART_LINE_CTRL

This enables the API for apps to control the serial line, such as baud rate, CTS and RTS.

Implementation is up to individual driver.

Says no if not sure.

CONFIG_UART_LITEUART

This option enables LiteUART serial driver.

CONFIG_UART_MCUMGR

Enable the mcumgr UART driver. This driver allows the application to communicate over UART using the mcumgr protocol for image upgrade and device management. The driver doesn’t inspect received data (as contrary to console UART driver) and all aspects of received protocol data are handled by an application provided callback.

CONFIG_UART_MCUMGR_ON_DEV_NAME

This option specifies the name of UART device to be used for mcumgr UART.

CONFIG_UART_MCUMGR_RX_BUF_COUNT

Specifies the number of the mcumgr UART receive buffers. Receive buffers hold received mcumgr fragments prior to reassembly. This setting’s value must satisfy the following relation: UART_MCUMGR_RX_BUF_COUNT * UART_MCUMGR_RX_BUF_SIZE >= MCUMGR_SMP_UART_MTU

CONFIG_UART_MCUMGR_RX_BUF_SIZE

Specifies the size of the mcumgr UART receive buffer, in bytes. This value must be large enough to accommodate any line sent by an mcumgr client.

CONFIG_UART_MCUX

Enable the MCUX uart driver.

CONFIG_UART_MCUX_0

Enable UART 0.

CONFIG_UART_MCUX_1

Enable UART 1.

CONFIG_UART_MCUX_2

Enable UART 2.

CONFIG_UART_MCUX_3

Enable UART 3.

CONFIG_UART_MCUX_4

Enable UART 4.

CONFIG_UART_MCUX_5

Enable UART 5.

CONFIG_UART_MCUX_FLEXCOMM

Enable the MCUX USART driver.

CONFIG_UART_MCUX_FLEXCOMM_0

Enable USART 0.

CONFIG_UART_MCUX_LPSCI

Enable the MCUX LPSCI driver.

CONFIG_UART_MCUX_LPSCI_0

Enable UART 0.

CONFIG_UART_MCUX_LPUART

Enable the MCUX LPUART driver.

CONFIG_UART_MCUX_LPUART_0

Enable UART 0.

CONFIG_UART_MCUX_LPUART_1

Enable UART 1.

CONFIG_UART_MCUX_LPUART_2

Enable UART 2.

CONFIG_UART_MCUX_LPUART_3

Enable UART 3.

CONFIG_UART_MCUX_LPUART_4

Enable UART 4.

CONFIG_UART_MIV

This option enables the Mi-V serial driver.

CONFIG_UART_MIV_PORT_0

This tells the driver to configure the UART port at boot, depending on the additional configuration options below.

CONFIG_UART_MSP432P4XX

This option enables the MSP432P4XX UART driver, for UART_0.

CONFIG_UART_NATIVE_POSIX

This enables a UART driver for the POSIX ARCH with up to 2 UARTs. For the first UART port, the driver can be configured to either connect to the terminal from which native_posix was run, or into one dedicated pseudoterminal for that UART.

CONFIG_UART_NATIVE_POSIX_PORT_1_ENABLE

Useful if you need to have another serial connection to host. This is used for example in PPP (Point-to-Point Protocol) implementation.

CONFIG_UART_NATIVE_POSIX_PORT_1_NAME

This is the device name for UART, and is included in the device struct.

CONFIG_UART_NRFX

Enable support for nrfx UART drivers for nRF MCU series. Peripherals with the same instance ID cannot be used together, e.g. UART_0 and UARTE_0.

CONFIG_UART_NS16550

This option enables the NS16550 serial driver. This driver can be used for the serial hardware available on x86 boards.

CONFIG_UART_NS16550_ACCESS_WORD_ONLY

In some case, e.g. ARC HS Development kit, the peripheral space of ns 16550 (DesignWare UART) only allows word access, byte access will raise exception.

CONFIG_UART_NS16550_DRV_CMD

This enables the API for apps to send commands to driver.

Says n if not sure.

CONFIG_UART_NS16550_LINE_CTRL

This enables the API for apps to control the serial line, such as CTS and RTS.

Says n if not sure.

CONFIG_UART_NS16550_PORT_0

This tells the driver to configure the UART port at boot, depending on the additional configure options below.

CONFIG_UART_NS16550_PORT_0_OPTIONS

Options used for port initialization.

CONFIG_UART_NS16550_PORT_1

This tells the driver to configure the UART port at boot, depending on the additional configure options below.

CONFIG_UART_NS16550_PORT_1_OPTIONS

Options used for port initialization.

CONFIG_UART_NS16550_PORT_2

This tells the driver to configure the UART port at boot, depending on the additional configure options below.

CONFIG_UART_NS16550_PORT_2_OPTIONS

Options used for port initialization.

CONFIG_UART_NS16550_PORT_3

This tells the driver to configure the UART port at boot, depending on the additional configure options below.

CONFIG_UART_NS16550_PORT_3_OPTIONS

Options used for port initialization.

CONFIG_UART_NS16750

This enables support for 64-bytes FIFO if UART controller is 16750.

CONFIG_UART_NSIM

This enables the UART driver for the MetaWare nSim simulator.

CONFIG_UART_PIPE

Enable pipe UART driver. This driver allows application to communicate over UART with custom defined protocol. Driver doesn’t inspect received data (as contrary to console UART driver) and all aspects of received protocol data are handled by application provided callback.

CONFIG_UART_PIPE_ON_DEV_NAME

This option specifies the name of UART device to be used for pipe UART.

CONFIG_UART_PL011

This option enables the UART driver for the PL011

CONFIG_UART_PL011_PORT0

Build the driver to utilize UART controller Port 0.

CONFIG_UART_PL011_PORT0_SHARED_IRQ

When interrupts fire, the shared IRQ driver is notified. Then the shared IRQ driver dispatches the interrupt to the UART driver.

CONFIG_UART_PL011_PORT1

Build the driver to utilize UART controller Port 1.

CONFIG_UART_PL011_PORT1_SHARED_IRQ

When interrupts fire, the shared IRQ driver is notified. Then the shared IRQ driver dispatches the interrupt to the UART driver.

CONFIG_UART_PL011_SHARED_IRQ

CONFIG_UART_PSOC6

This option enables the UART driver for PSoC6 family of processors.

CONFIG_UART_PSOC6_UART_5

Enable support for UART_5 on port 5 in the driver.

CONFIG_UART_PSOC6_UART_6

Enable support for UART_6 on port 12 in the driver.

CONFIG_UART_RTT

This option enables access RTT channel as UART device.

CONFIG_UART_RTT_0

Enable UART on (default) RTT channel 0. Default channel has to be configured in non-blocking skip mode.

CONFIG_UART_RTT_1

Enable UART on RTT channel 1

CONFIG_UART_RTT_1_RX_BUFFER_SIZE

Size of the RTT down buffer for UART 1 reception.

CONFIG_UART_RTT_1_TX_BUFFER_SIZE

Size of the RTT up buffer for UART 1 transmission.

CONFIG_UART_RTT_2

Enable UART on RTT channel 2

CONFIG_UART_RTT_2_RX_BUFFER_SIZE

Size of the RTT down buffer for UART 2 reception.

CONFIG_UART_RTT_2_TX_BUFFER_SIZE

Size of the RTT up buffer for UART 2 transmission.

CONFIG_UART_RTT_3

Enable UART on RTT channel 3

CONFIG_UART_RTT_3_RX_BUFFER_SIZE

Size of the RTT down buffer for UART 3 reception.

CONFIG_UART_RTT_3_TX_BUFFER_SIZE

Size of the RTT up buffer for UART 3 transmission.

CONFIG_UART_RTT_DRIVER

CONFIG_UART_RV32M1_LPUART

Enable the RV32M1 LPUART driver.

CONFIG_UART_RV32M1_LPUART_0

Enable UART 0.

CONFIG_UART_RV32M1_LPUART_1

Enable UART 1.

CONFIG_UART_RV32M1_LPUART_2

Enable UART 2.

CONFIG_UART_RV32M1_LPUART_3

Enable UART 3.

CONFIG_UART_SAM

This option enables the UARTx driver for Atmel SAM MCUs.

CONFIG_UART_SAM0

This option enables the SERCOMx USART driver for Atmel SAM0 MCUs.

CONFIG_UART_SAM_PORT_0

Enable UART0 at boot.

CONFIG_UART_SAM_PORT_1

Enable UART1 at boot.

CONFIG_UART_SAM_PORT_1_PIN_TX_PA4

PA4

CONFIG_UART_SAM_PORT_1_PIN_TX_PA6

PA6

CONFIG_UART_SAM_PORT_1_PIN_TX_PD26

PD26

CONFIG_UART_SAM_PORT_2

Enable UART2 at boot

CONFIG_UART_SAM_PORT_3

Enable UART3 at boot

CONFIG_UART_SAM_PORT_3_PIN_TX_PD30

PD30

CONFIG_UART_SAM_PORT_3_PIN_TX_PD31

PD31

CONFIG_UART_SAM_PORT_4

Enable UART4 at boot

CONFIG_UART_SAM_PORT_4_PIN_TX_PD19

PD19

CONFIG_UART_SAM_PORT_4_PIN_TX_PD3

PD3

CONFIG_UART_SIFIVE

This option enables the SiFive Freedom serial driver.

CONFIG_UART_SIFIVE_PORT_0

This tells the driver to configure the UART port at boot, depending on the additional configure options below.

CONFIG_UART_SIFIVE_PORT_0_IRQ_PRIORITY

Port 0 Interrupt Priority

CONFIG_UART_SIFIVE_PORT_0_RXCNT_IRQ

Port 0 RX Threshold at which the RX FIFO interrupt triggers.

CONFIG_UART_SIFIVE_PORT_0_TXCNT_IRQ

Port 0 TX Threshold at which the TX FIFO interrupt triggers.

CONFIG_UART_SIFIVE_PORT_1

This tells the driver to configure the UART port at boot, depending on the additional configure options below.

CONFIG_UART_SIFIVE_PORT_1_IRQ_PRIORITY

Port 1 Interrupt Priority

CONFIG_UART_SIFIVE_PORT_1_RXCNT_IRQ

Port 1 RX Threshold at which the RX FIFO interrupt triggers.

CONFIG_UART_SIFIVE_PORT_1_TXCNT_IRQ

Port 1 TX Threshold at which the TX FIFO interrupt triggers.

CONFIG_UART_STELLARIS

This option enables the Stellaris serial driver. This specific driver can be used for the serial hardware available at the Texas Instrument LM3S6965 board.

CONFIG_UART_STELLARIS_PORT_0

This tells the driver to configure the UART port at boot, depending on the additional configure options below.

CONFIG_UART_STELLARIS_PORT_1

This tells the driver to configure the UART port at boot, depending on the additional configure options below.

CONFIG_UART_STELLARIS_PORT_2

This tells the driver to configure the UART port at boot, depending on the additional configure options below.

CONFIG_UART_STM32

This option enables the UART driver for STM32 family of processors. Say y if you wish to use serial port on STM32 MCU.

CONFIG_UART_XLNX_PS

This option enables the UART driver for Xilinx MPSoC platforms.

CONFIG_USART_SAM

This option enables the USARTx driver for Atmel SAM MCUs.

CONFIG_USART_SAM_PORT_0

Enable USART0 at boot

CONFIG_USART_SAM_PORT_1

Enable USART1 at boot

CONFIG_USART_SAM_PORT_2

Enable USART2 at boot

CONFIG_USB

Enable USB drivers.

CONFIG_USB_DC_NXP_EHCI

Kinetis and RT EHCI USB Device Controller Driver.

CONFIG_USB_DC_SAM

SAM family USB HS device controller Driver.

CONFIG_USB_DC_SAM0

SAM0 family USB device controller Driver.

CONFIG_USB_DC_STM32

Enable USB support on the STM32 F0, F1, F2, F3, F4, F7, L0, L4 and G4 family of processors.

CONFIG_USB_DC_STM32_DISCONN_ENABLE

Say Y if your board uses USB DISCONNECT pin to enable the pull-up resistor on USB DP.

CONFIG_USB_DEVICE_DRIVER

CONFIG_USB_DW

Designware USB Device Controller Driver.

CONFIG_USB_DW_USB_2_0

Indicates whether or not USB specification version 2.0 is supported

CONFIG_USB_KINETIS

Kinetis USB Device Controller Driver.

CONFIG_USB_NATIVE_POSIX

Native Posix USB Device Controller Driver.

CONFIG_USB_NRFX

nRF USB Device Controller Driver

CONFIG_USB_NRFX_EVT_QUEUE_SIZE

Size of the driver’s internal event queue. Required size will depend on number of endpoints (class instances) in use.

CONFIG_USB_NRFX_WORK_QUEUE_STACK_SIZE

Size of the stack for the work queue thread that is used in the driver for handling the events from the USBD ISR, i.e. executing endpoint callbacks and providing proper notifications to the USB device stack.

CONFIG_USB_UART_CONSOLE

Enable this option to use the USB UART for console output. The output can be viewed from the USB host via /dev/ttyACM* port. Note that console inputs from the USB UART are not functional yet. Also since the USB layer currently doesn’t support multiple interfaces, this shouldn’t be selected in conjunction with, say, USB Mass Storage.

CONFIG_USB_UART_DTR_WAIT

Enable this option to use flow control on the console. The uart console waits until the DTR is asserted by the host. Note: Disabling this might lead to missing console prints.

CONFIG_VEXRISCV_LITEX_IRQ

IRQ implementation for LiteX VexRiscv

CONFIG_VIDEO

Enable support for the VIDEO.

CONFIG_VIDEO_BUFFER_POOL_ALIGN

Alignment of the video pool’s buffer

CONFIG_VIDEO_BUFFER_POOL_NUM_MAX

Number of maximum sized buffer in the video pool

CONFIG_VIDEO_BUFFER_POOL_SZ_MAX

Size of the largest buffer in the video pool

CONFIG_VIDEO_MCUX_CSI

NXP MCUX CMOS Sensor Interface (CSI) driver

CONFIG_VIDEO_MT9M114

Enable driver for MT9M114 CMOS digital image sensor device.

CONFIG_VIDEO_SW_GENERATOR

Enable video pattern generator (for testing purposes).

CONFIG_VL53L0X

Enable driver for VL53L0X I2C-based time of flight sensor.

CONFIG_VL53L0X_PROXIMITY_THRESHOLD

Threshold used for proximity detection when sensor is used with SENSOR_CHAN_PROX.

CONFIG_WATCHDOG

Include support for watchdogs.

CONFIG_WDOG_CMSDK_APB

Enable CMSDK APB Watchdog (WDOG_CMSDK_APB) Driver for ARM family of MCUs.

CONFIG_WDOG_CMSDK_APB_START_AT_BOOT

Enable this setting to allow WDOG to be automatically started during device initialization. Note that once WDOG is started it must be reloaded before the counter reaches 0, otherwise the MCU will be reset.

CONFIG_WDT0_ESP32_IRQ

Set the IRQ line used by the WDT device. Very few lines can be chosen here, as it must be a level 4 interrupt.

CONFIG_WDT1_ESP32_IRQ

Set the IRQ line used by the WDT device. Very few lines can be chosen here, as it must be a level 4 interrupt.

CONFIG_WDT_DISABLE_AT_BOOT

Disable watchdog at Zephyr system startup for the SoCs that enable the watchdog by default after reset.

Note that disabling this configuration option does not enable the watchdog for the SoCs that boot with the watchdog disabled.

CONFIG_WDT_ESP32

Enable WDT driver for ESP32.

CONFIG_WDT_MCUX_WDOG

Enable the mcux wdog driver.

CONFIG_WDT_MCUX_WDOG32

Enable the mcux wdog32 driver.

CONFIG_WDT_MULTISTAGE

Enable multistage operation of watchdog timeouts.

CONFIG_WDT_NRFX

Enable support for nrfx WDT driver for nRF MCU series.

CONFIG_WDT_SAM

Enable WDT driver for Atmel SAM MCUs.

CONFIG_WDT_SAM0

Enable WDT driver for Atmel SAM0 MCUs.

CONFIG_WDT_XEC

Enable WDT driver for Microchip XEC MCU series.

CONFIG_WIFI

add support for Wi-Fi Drivers

CONFIG_WIFI_ESWIFI

Inventek eS-WiFi support

CONFIG_WIFI_ESWIFI_NAME

Driver name

CONFIG_WIFI_ESWIFI_THREAD_PRIO

This option sets the priority of the esWiFi threads. Do not touch it unless you know what you are doing.

CONFIG_WIFI_INIT_PRIORITY

Wi-Fi device driver initialization priority. Do not mess with it unless you know what you are doing. Note that the priority needs to be lower than the net stack so that it can start before the networking sub-system.

CONFIG_WIFI_OFFLOAD

Enable support for Full-MAC Wi-Fi devices.

CONFIG_WIFI_SIMPLELINK

SimpleLink Wi-Fi driver support

CONFIG_WIFI_SIMPLELINK_FAST_CONNECT_TIMEOUT

SimpleLink uses the “FastConnect” feature to reconnect to the previously connected AP on startup. Should the Wi-Fi connection timeout, the SimpleLink driver will fail to initialize, and LOG an error.

CONFIG_WIFI_SIMPLELINK_MAX_PACKET_SIZE

Set the maximum size of a network packet going through the chip. This sets the size of each buffer, in each buffer pool. Do not modify it unless you know what you are doing.

CONFIG_WIFI_SIMPLELINK_MAX_SCAN_RETRIES

The number of times, separated by a one second interval, to retry a request for the network list.

CONFIG_WIFI_SIMPLELINK_NAME

Driver name

CONFIG_WIFI_SIMPLELINK_SCAN_COUNT

The number of results to request on a Wi-Fi scan operation. Actual number returned may be less. Maximum is 30.

CONFIG_WIFI_WINC1500

WINC1500 driver support

CONFIG_WIFI_WINC1500_BUF_CTR

Set the number of buffer the driver will have access to in each of its buffer pools.

CONFIG_WIFI_WINC1500_GPIO_SPI_CS

This option is useful if one needs to manage SPI CS through a GPIO pin to by-pass the SPI controller’s CS logic.

CONFIG_WIFI_WINC1500_MAX_PACKET_SIZE

Set the maximum size of a network packet going through the chip. This sets the size of each buffer, in each buffer pools. Do not modify it unless you know what you are doing.

CONFIG_WIFI_WINC1500_NAME

Driver name

CONFIG_WIFI_WINC1500_OFFLOAD_MAX_SOCKETS

Set the number of sockets that can be managed through the driver and the chip.

CONFIG_WIFI_WINC1500_REGION_ASIA

Region Asia

CONFIG_WIFI_WINC1500_REGION_EUROPE

Region Europe

CONFIG_WIFI_WINC1500_REGION_NORTH_AMERICA

Region North America

CONFIG_WIFI_WINC1500_THREAD_PRIO

This option sets the priority of the thread handling WINC1500 HAL callbacks. Do not touch it unless you know what you are doing.

CONFIG_WIFI_WINC1500_THREAD_STACK_SIZE

This option sets the size of the stack used by the thread handling WINC1500 HAL callbacks. Do not touch it unless you know what you are doing.

CONFIG_WS2812B_SW

A software-based (bit-banging) LED strip driver for daisy chains of WS2812B devices. This driver implements the signal sending with software-based bit-banging. If a more efficient option, such as SPI, is available, another driver is recommended to be used.

CONFIG_WS2812B_SW_GPIO_NAME

GPIO port name.

CONFIG_WS2812B_SW_GPIO_PIN

GPIO pin number that the LED strip is connected to.

CONFIG_WS2812B_SW_NAME

Device name for WS2812B LED strip.

CONFIG_WS2812_BLU_ORDER

If the blue channel is shifted out first, specify 0. If second, specify 1, and so on.

CONFIG_WS2812_GRN_ORDER

If the green channel is shifted out first, specify 0. If second, specify 1, and so on.

CONFIG_WS2812_HAS_WHITE_CHANNEL

If the chipset has a white channel, say y. White channels are not used by the driver, but must be declared if expected by the chip.

CONFIG_WS2812_RED_ORDER

If the red channel is shifted out first, specify 0. If second, specify 1, and so on.

CONFIG_WS2812_STRIP

Enable LED strip driver for daisy chains of WS2812-ish (or WS2812B, WS2813, SK6812, or compatible) devices. These devices have a one-wire communications interface which encodes bits using pulses. Short pulses indicate zero bits, and long pulses indicate ones; refer to the chip datasheets for precise specifications. To implement this in a multitasking operating system, this driver generates the pulses using a SPI peripheral.

CONFIG_WS2812_STRIP_MAX_PIXELS

Set this to the maximum number of pixels you need to control at once. There is an 8x memory penalty associated with each increment of this value, so it’s worth optimizing.

CONFIG_WS2812_STRIP_ONE_FRAME

When shifted out at the configured clock frequency, this must generate a pulse whose width fits within the chipset specifications for T1H, and whose interpulse timing meets low times. It is recommended that the first and last bits in the frame be zero; this “encourages” SPI IPs to leave MOSI low between frames.

CONFIG_WS2812_STRIP_ZERO_FRAME

When shifted out at the configured clock frequency, this must generate a pulse whose width fits within the chipset specifications for T0H, and whose interpulse timing meets low times. It is recommended that the first and last bits in the frame be zero; this “encourages” SPI IPs to leave MOSI low between frames.

CONFIG_WS2812_WHT_ORDER

If the blue channel is shifted out first, specify 0. If second, specify 1, and so on.

CONFIG_WWDG_STM32

Enable WWDG driver for STM32 line of MCUs

CONFIG_X2APIC

If your local APIC supports x2APIC mode, turn this on.

CONFIG_XLNX_PSTTC_TIMER

This module implements a kernel device driver for the Xilinx ZynqMP platform provides the standard “system clock driver” interfaces. If unchecked, no timer will be used.

CONFIG_XLNX_PSTTC_TIMER_INDEX

This is the index of TTC timer picked to provide system clock.

CONFIG_XTENSA_CONSOLE_INIT_PRIORITY

Device driver initialization priority.

CONFIG_XTENSA_SIM_CONSOLE

Use simulator console to print messages.

CONFIG_XTENSA_TIMER

Enables a system timer driver for Xtensa based on the CCOUNT and CCOMPARE special registers.

CONFIG_XTENSA_TIMER_ID

Index of the CCOMPARE register (and associated interrupt) used for the system timer. Xtensa CPUs have hard-configured interrupt priorities associated with each timer, and some of them can be unmaskable (and thus not usable by OS code that need synchronization, like the timer subsystem!). Choose carefully. Generally you want the timer with the highest priority maskable interrupt.