CONFIG_CLOCK_STM32_PLL_Q_DIVISOR

PLL division factor for USB OTG FS, SDIO and RNG clocks

Division factor for OTG FS, SDIO and RNG clocks

PLL Q Divisor

Type: int

Help

The USB OTG FS requires a 48MHz clock to work correctly. SDIO and RNG need a frequency lower than or equal to 48 MHz to work correctly. Allowed values: 2-15

Help

The USB OTG FS requires a 48MHz clock to work correctly. SDIO and RNG need a frequency lower than or equal to 48 MHz to work correctly. Allowed values: 2-15

Help

PLL Q Output divisor, allowed values: 0, 2, 4, 6, 8.

Kconfig definitions

At boards/arm/disco_l475_iot1/Kconfig.defconfig:51

Included via Kconfig:10Kconfig.zephyr:21

Menu path: (top menu)

config CLOCK_STM32_PLL_Q_DIVISOR
    int
    default 2 if CLOCK_STM32_PLL_SRC_HSI && CLOCK_STM32_SYSCLK_SRC_PLL && BOARD_DISCO_L475_IOT1
    depends on CLOCK_STM32_PLL_SRC_HSI && CLOCK_STM32_SYSCLK_SRC_PLL && BOARD_DISCO_L475_IOT1

At drivers/clock_control/Kconfig.stm32:226

Included via Kconfig:10Kconfig.zephyr:35drivers/Kconfig:54drivers/clock_control/Kconfig:30

Menu path: (top menu) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control

config CLOCK_STM32_PLL_Q_DIVISOR
    int
    prompt "PLL division factor for USB OTG FS, SDIO and RNG clocks" if CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32F2X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    range 2 15 if CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32F2X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    default 5 if CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32F2X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    depends on CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32F2X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    help
      The USB OTG FS requires a 48MHz clock to work correctly. SDIO and RNG
      need a frequency lower than or equal to 48 MHz to work correctly.
      Allowed values: 2-15

At drivers/clock_control/Kconfig.stm32:291

Included via Kconfig:10Kconfig.zephyr:35drivers/Kconfig:54drivers/clock_control/Kconfig:30

Menu path: (top menu) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control

config CLOCK_STM32_PLL_Q_DIVISOR
    int
    prompt "Division factor for OTG FS, SDIO and RNG clocks" if CLOCK_STM32_SYSCLK_SRC_PLL && (SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X) && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    range 2 15 if CLOCK_STM32_SYSCLK_SRC_PLL && (SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X) && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    default 7 if CLOCK_STM32_SYSCLK_SRC_PLL && (SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X) && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    depends on CLOCK_STM32_SYSCLK_SRC_PLL && (SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X) && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    help
      The USB OTG FS requires a 48MHz clock to work correctly. SDIO and RNG
      need a frequency lower than or equal to 48 MHz to work correctly.
      Allowed values: 2-15

At drivers/clock_control/Kconfig.stm32:352

Included via Kconfig:10Kconfig.zephyr:35drivers/Kconfig:54drivers/clock_control/Kconfig:30

Menu path: (top menu) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control

config CLOCK_STM32_PLL_Q_DIVISOR
    int
    prompt "PLL Q Divisor" if CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32L4X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    range 0 8 if CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32L4X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    default 2 if CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32L4X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    depends on CLOCK_STM32_SYSCLK_SRC_PLL && SOC_SERIES_STM32L4X && CLOCK_CONTROL_STM32_CUBE && SOC_FAMILY_STM32 && CLOCK_CONTROL
    help
      PLL Q Output divisor, allowed values: 0, 2, 4, 6, 8.

(Definitions include propagated dependencies, including from if’s and menus.)